mult242.vhd

VHDL设计FIR滤波器 基于QUARTUS和MATLAB

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult242 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (8 DOWNTO 0);
 Dout :  OUT SIGNED (15 DOWNTO 0));
END mult242;
--128+64+32+16+2
ARCHITECTURE a OF mult242 IS
SIGNAL s1 : SIGNED (15 DOWNTO 0);
SIGNAL s2 : SIGNED (14 DOWNTO 0);
SIGNAL s3 : SIGNED (13 DOWNTO 0);
SIGNAL s4 : SIGNED (12 DOWNTO 0);
SIGNAL s5 : SIGNED (15 DOWNTO 0);
BEGIN
P1:process(Din)
BEGIN
s1(15 DOWNTO 7)<=Din;
s1( 6 DOWNTO 0)<="0000000";
s2(14 DOWNTO 6)<=Din;
s2( 5 DOWNTO 0)<="000000";
s3(13 DOWNTO 5)<=Din;
s3( 4 DOWNTO 0)<="00000";
s4(12 DOWNTO 4)<=Din;
s4( 3 DOWNTO 0)<="0000";
if Din(8)='0' then 
s5<=('0'&s1(15 downto 1))+("00"&s2(14 DOWNTO 1))+("000"&s3(13 DOWNTO 1))+("0000"&s4(12 DOWNTO 1))+("0000000"&Din);

else 
s5<=('1'&s1(15 downto 1))+("11"&s2(14 DOWNTO 1))+("111"&s3(13 DOWNTO 1))+("1111"&s4(12 DOWNTO 1))+("1111111"&Din);

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s5;
end if;
END PROCESS;
END a;