sopi.vhd

来自「VHDL spi源代码内核介绍」· VHDL 代码 · 共 32 行

library ieee;--------8 bits  parallel input serial output
use ieee.std_logic_1164.all;
entity sopi is
  port (clk :in std_logic;
        load:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        data_out:out std_logic);
        
end sopi;
architecture a of sopi is
  signal q: std_logic_vector(7 downto 0);
begin 
  process(load,clk)
  begin 
    if load='0'then
      q<=data_in;
    elsif clk 'event and clk='1'then 
     q(1)<=q(0);
     for i in 2 to 7 loop
       q(i)<=q(i-1);
     end loop;
    end if;
  end process;
 process(load,clk)
  begin 
    if load='0'then
      data_out<='0';
    elsif clk 'event and clk='1'then 
      data_out<=q(7);
    end if;
  end process;
end a;