pro3.fit.eqn

VHDL spi源代码内核介绍

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_q[7] is sipo:inst1|q[7] at LC_X34_Y20_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_q[7]_lut_out = GND;
C1_q[7] = DFFEAS(C1_q[7]_lut_out, !GLOBAL(clk), VCC, , , C1_q[6], , , VCC);


--C1_q[6] is sipo:inst1|q[6] at LC_X34_Y20_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_q[6]_lut_out = GND;
C1_q[6] = DFFEAS(C1_q[6]_lut_out, !GLOBAL(clk), VCC, , , C1_q[5], , , VCC);


--C1_q[5] is sipo:inst1|q[5] at LC_X34_Y20_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_q[5]_lut_out = GND;
C1_q[5] = DFFEAS(C1_q[5]_lut_out, !GLOBAL(clk), VCC, , , C1_q[4], , , VCC);


--C1_q[4] is sipo:inst1|q[4] at LC_X34_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_q[4]_lut_out = GND;
C1_q[4] = DFFEAS(C1_q[4]_lut_out, !GLOBAL(clk), VCC, , , C1_q[3], , , VCC);


--C1_q[3] is sipo:inst1|q[3] at LC_X34_Y20_N9
--operation mode is normal

C1_q[3]_lut_out = C1_q[2];
C1_q[3] = DFFEAS(C1_q[3]_lut_out, !GLOBAL(clk), VCC, , , , , , );


--C1_q[2] is sipo:inst1|q[2] at LC_X34_Y20_N3
--operation mode is normal

C1_q[2]_lut_out = C1_q[1];
C1_q[2] = DFFEAS(C1_q[2]_lut_out, !GLOBAL(clk), VCC, , , , , , );


--C1_q[1] is sipo:inst1|q[1] at LC_X34_Y20_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_q[1]_lut_out = GND;
C1_q[1] = DFFEAS(C1_q[1]_lut_out, !GLOBAL(clk), VCC, , , C1_q[0], , , VCC);


--C1_q[0] is sipo:inst1|q[0] at LC_X34_Y20_N8
--operation mode is normal

C1_q[0]_lut_out = miso;
C1_q[0] = DFFEAS(C1_q[0]_lut_out, !GLOBAL(clk), VCC, , , , , , );


--B1_data_out is sopi:inst|data_out at LC_X34_Y2_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_out_lut_out = GND;
B1_data_out = DFFEAS(B1_data_out_lut_out, GLOBAL(clk), GLOBAL(load), , , B1_q[7], , , VCC);


--B1_q[7] is sopi:inst|q[7] at LC_X34_Y2_N7
--operation mode is normal

B1_q[7]_lut_out = B1_q[6];
B1_q[7] = DFFEAS(B1_q[7]_lut_out, GLOBAL(clk), VCC, , , data_in[7], !GLOBAL(load), , );


--B1_q[6] is sopi:inst|q[6] at LC_X34_Y2_N4
--operation mode is normal

B1_q[6]_lut_out = B1_q[5];
B1_q[6] = DFFEAS(B1_q[6]_lut_out, GLOBAL(clk), VCC, , , data_in[6], !GLOBAL(load), , );


--B1_q[5] is sopi:inst|q[5] at LC_X34_Y2_N2
--operation mode is normal

B1_q[5]_lut_out = B1_q[4];
B1_q[5] = DFFEAS(B1_q[5]_lut_out, GLOBAL(clk), VCC, , , data_in[5], !GLOBAL(load), , );


--B1_q[4] is sopi:inst|q[4] at LC_X34_Y2_N9
--operation mode is normal

B1_q[4]_lut_out = B1_q[3];
B1_q[4] = DFFEAS(B1_q[4]_lut_out, GLOBAL(clk), VCC, , , data_in[4], !GLOBAL(load), , );


--B1_q[3] is sopi:inst|q[3] at LC_X34_Y2_N0
--operation mode is normal

B1_q[3]_lut_out = B1_q[2];
B1_q[3] = DFFEAS(B1_q[3]_lut_out, GLOBAL(clk), VCC, , , data_in[3], !GLOBAL(load), , );


--B1_q[2] is sopi:inst|q[2] at LC_X34_Y2_N8
--operation mode is normal

B1_q[2]_lut_out = B1_q[1];
B1_q[2] = DFFEAS(B1_q[2]_lut_out, GLOBAL(clk), VCC, , , data_in[2], !GLOBAL(load), , );


--B1_q[0] is sopi:inst|q[0] at LC_X34_Y2_N5
--operation mode is normal

B1_q[0] = GLOBAL(load) & (B1_q[0]) # !GLOBAL(load) & data_in[0];

--B1_q[1] is sopi:inst|q[1] at LC_X34_Y2_N5
--operation mode is normal

B1_q[1] = DFFEAS(B1_q[0], GLOBAL(clk), VCC, , , data_in[1], !GLOBAL(load), , );


--ssl is ssl at PIN_121
--operation mode is input

ssl = INPUT();


--clk is clk at PIN_122
--operation mode is input

clk = INPUT();


--miso is miso at PIN_123
--operation mode is input

miso = INPUT();


--load is load at PIN_29
--operation mode is input

load = INPUT();


--data_in[7] is data_in[7] at PIN_116
--operation mode is input

data_in[7] = INPUT();


--data_in[6] is data_in[6] at PIN_126
--operation mode is input

data_in[6] = INPUT();


--data_in[5] is data_in[5] at PIN_125
--operation mode is input

data_in[5] = INPUT();


--data_in[4] is data_in[4] at PIN_118
--operation mode is input

data_in[4] = INPUT();


--data_in[3] is data_in[3] at PIN_127
--operation mode is input

data_in[3] = INPUT();


--data_in[2] is data_in[2] at PIN_128
--operation mode is input

data_in[2] = INPUT();


--data_in[1] is data_in[1] at PIN_120
--operation mode is input

data_in[1] = INPUT();


--data_in[0] is data_in[0] at PIN_119
--operation mode is input

data_in[0] = INPUT();


--mosi is mosi at PIN_124
--operation mode is output

mosi_tri_out = TRI(B1_data_out, ssl);
mosi = OUTPUT(mosi_tri_out);


--d_out[7] is d_out[7] at PIN_178
--operation mode is output

d_out[7] = OUTPUT(C1_q[7]);


--d_out[6] is d_out[6] at PIN_176
--operation mode is output

d_out[6] = OUTPUT(C1_q[6]);


--d_out[5] is d_out[5] at PIN_181
--operation mode is output

d_out[5] = OUTPUT(C1_q[5]);


--d_out[4] is d_out[4] at PIN_179
--operation mode is output

d_out[4] = OUTPUT(C1_q[4]);


--d_out[3] is d_out[3] at PIN_183
--operation mode is output

d_out[3] = OUTPUT(C1_q[3]);


--d_out[2] is d_out[2] at PIN_180
--operation mode is output

d_out[2] = OUTPUT(C1_q[2]);


--d_out[1] is d_out[1] at PIN_182
--operation mode is output

d_out[1] = OUTPUT(C1_q[1]);


--d_out[0] is d_out[0] at PIN_177
--operation mode is output

d_out[0] = OUTPUT(C1_q[0]);