count24_04.tan.qmsg

24进制倒计时 24进制倒计时用VHDL编写

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt\[0\]~reg0 cnt\[3\]~reg0 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"cnt\[0\]~reg0\" and destination register \"cnt\[3\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.306 ns + Longest register register " "Info: + Longest register to register delay is 3.306 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\]~reg0 1 REG LC_X1_Y24_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y24_N1; Fanout = 5; REG Node = 'cnt\[0\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { cnt[0]~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.432 ns) 1.516 ns add~78COUT1_102 2 COMB LC_X1_Y24_N5 2 " "Info: 2: + IC(1.084 ns) + CELL(0.432 ns) = 1.516 ns; Loc. = LC_X1_Y24_N5; Fanout = 2; COMB Node = 'add~78COUT1_102'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.516 ns" { cnt[0]~reg0 add~78COUT1_102 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.596 ns add~83COUT1 3 COMB LC_X1_Y24_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.596 ns; Loc. = LC_X1_Y24_N6; Fanout = 2; COMB Node = 'add~83COUT1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.080 ns" { add~78COUT1_102 add~83COUT1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.676 ns add~88COUT1_103 4 COMB LC_X1_Y24_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.676 ns; Loc. = LC_X1_Y24_N7; Fanout = 2; COMB Node = 'add~88COUT1_103'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.080 ns" { add~83COUT1 add~88COUT1_103 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.284 ns add~91 5 COMB LC_X1_Y24_N8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 2.284 ns; Loc. = LC_X1_Y24_N8; Fanout = 1; COMB Node = 'add~91'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.608 ns" { add~88COUT1_103 add~91 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.607 ns) 3.306 ns cnt\[3\]~reg0 6 REG LC_X1_Y24_N3 5 " "Info: 6: + IC(0.415 ns) + CELL(0.607 ns) = 3.306 ns; Loc. = LC_X1_Y24_N3; Fanout = 5; REG Node = 'cnt\[3\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.022 ns" { add~91 cnt[3]~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.807 ns ( 54.66 % ) " "Info: Total cell delay = 1.807 ns ( 54.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.499 ns ( 45.34 % ) " "Info: Total interconnect delay = 1.499 ns ( 45.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.306 ns" { cnt[0]~reg0 add~78COUT1_102 add~83COUT1 add~88COUT1_103 add~91 cnt[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.306 ns" { cnt[0]~reg0 add~78COUT1_102 add~83COUT1 add~88COUT1_103 add~91 cnt[3]~reg0 } { 0.000ns 1.084ns 0.000ns 0.000ns 0.000ns 0.415ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.608ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.245 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { clk } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns cnt\[3\]~reg0 2 REG LC_X1_Y24_N3 5 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y24_N3; Fanout = 5; REG Node = 'cnt\[3\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.776 ns" { clk cnt[3]~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk cnt[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 cnt[3]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.245 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { clk } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns cnt\[0\]~reg0 2 REG LC_X1_Y24_N1 5 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y24_N1; Fanout = 5; REG Node = 'cnt\[0\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.776 ns" { clk cnt[0]~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk cnt[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 cnt[0]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk cnt[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 cnt[3]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk cnt[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 cnt[0]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.306 ns" { cnt[0]~reg0 add~78COUT1_102 add~83COUT1 add~88COUT1_103 add~91 cnt[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.306 ns" { cnt[0]~reg0 add~78COUT1_102 add~83COUT1 add~88COUT1_103 add~91 cnt[3]~reg0 } { 0.000ns 1.084ns 0.000ns 0.000ns 0.000ns 0.415ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.608ns 0.607ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk cnt[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 cnt[3]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk cnt[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 cnt[0]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { cnt[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { cnt[3]~reg0 } {  } {  } } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "y~reg0 clr clk 3.712 ns register " "Info: tsu for register \"y~reg0\" (data pin = \"clr\", clock pin = \"clk\") is 3.712 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.920 ns + Longest pin register " "Info: + Longest pin to register delay is 6.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clr 1 PIN PIN_7 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 6; PIN Node = 'clr'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { clr } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.973 ns) + CELL(0.478 ns) 6.920 ns y~reg0 2 REG LC_X2_Y24_N3 2 " "Info: 2: + IC(4.973 ns) + CELL(0.478 ns) = 6.920 ns; Loc. = LC_X2_Y24_N3; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "5.451 ns" { clr y~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 28.14 % ) " "Info: Total cell delay = 1.947 ns ( 28.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.973 ns ( 71.86 % ) " "Info: Total interconnect delay = 4.973 ns ( 71.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "6.920 ns" { clr y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.920 ns" { clr clr~out0 y~reg0 } { 0.000ns 0.000ns 4.973ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.245 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { clk } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns y~reg0 2 REG LC_X2_Y24_N3 2 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y24_N3; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.776 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "6.920 ns" { clr y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.920 ns" { clr clr~out0 y~reg0 } { 0.000ns 0.000ns 4.973ns } { 0.000ns 1.469ns 0.478ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y y~reg0 7.444 ns register " "Info: tco from clock \"clk\" to destination pin \"y\" through register \"y~reg0\" is 7.444 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.245 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { clk } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns y~reg0 2 REG LC_X2_Y24_N3 2 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y24_N3; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.776 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.975 ns + Longest register pin " "Info: + Longest register to pin delay is 3.975 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y~reg0 1 REG LC_X2_Y24_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y24_N3; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { y~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.851 ns) + CELL(2.124 ns) 3.975 ns y 2 PIN PIN_11 0 " "Info: 2: + IC(1.851 ns) + CELL(2.124 ns) = 3.975 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'y'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.975 ns" { y~reg0 y } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 53.43 % ) " "Info: Total cell delay = 2.124 ns ( 53.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.851 ns ( 46.57 % ) " "Info: Total interconnect delay = 1.851 ns ( 46.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.975 ns" { y~reg0 y } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.975 ns" { y~reg0 y } { 0.000ns 1.851ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.975 ns" { y~reg0 y } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.975 ns" { y~reg0 y } { 0.000ns 1.851ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "y~reg0 clr clk -3.660 ns register " "Info: th for register \"y~reg0\" (data pin = \"clr\", clock pin = \"clk\") is -3.660 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.245 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { clk } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns y~reg0 2 REG LC_X2_Y24_N3 2 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y24_N3; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.776 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.920 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clr 1 PIN PIN_7 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 6; PIN Node = 'clr'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { clr } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.973 ns) + CELL(0.478 ns) 6.920 ns y~reg0 2 REG LC_X2_Y24_N3 2 " "Info: 2: + IC(4.973 ns) + CELL(0.478 ns) = 6.920 ns; Loc. = LC_X2_Y24_N3; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "5.451 ns" { clr y~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 28.14 % ) " "Info: Total cell delay = 1.947 ns ( 28.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.973 ns ( 71.86 % ) " "Info: Total interconnect delay = 4.973 ns ( 71.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "6.920 ns" { clr y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.920 ns" { clr clr~out0 y~reg0 } { 0.000ns 0.000ns 4.973ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "3.245 ns" { clk y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "6.920 ns" { clr y~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.920 ns" { clr clr~out0 y~reg0 } { 0.000ns 0.000ns 4.973ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}