count24_04.fit.qmsg

24进制倒计时 24进制倒计时用VHDL编写

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cnt " "Warning: Node \"cnt\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "cnt" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.722 ns register register " "Info: Estimated most critical path is register to register delay of 2.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\]~reg0 1 REG LAB_X1_Y24 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y24; Fanout = 5; REG Node = 'cnt\[0\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "" { cnt[0]~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.575 ns) 1.045 ns add~78COUT1_102 2 COMB LAB_X1_Y24 2 " "Info: 2: + IC(0.470 ns) + CELL(0.575 ns) = 1.045 ns; Loc. = LAB_X1_Y24; Fanout = 2; COMB Node = 'add~78COUT1_102'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "1.045 ns" { cnt[0]~reg0 add~78COUT1_102 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.125 ns add~83COUT1 3 COMB LAB_X1_Y24 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.125 ns; Loc. = LAB_X1_Y24; Fanout = 2; COMB Node = 'add~83COUT1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.080 ns" { add~78COUT1_102 add~83COUT1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.205 ns add~88COUT1_103 4 COMB LAB_X1_Y24 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.205 ns; Loc. = LAB_X1_Y24; Fanout = 2; COMB Node = 'add~88COUT1_103'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.080 ns" { add~83COUT1 add~88COUT1_103 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.285 ns add~93COUT1_104 5 COMB LAB_X1_Y24 1 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.285 ns; Loc. = LAB_X1_Y24; Fanout = 1; COMB Node = 'add~93COUT1_104'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.080 ns" { add~88COUT1_103 add~93COUT1_104 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.893 ns add~96 6 COMB LAB_X1_Y24 1 " "Info: 6: + IC(0.000 ns) + CELL(0.608 ns) = 1.893 ns; Loc. = LAB_X1_Y24; Fanout = 1; COMB Node = 'add~96'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.608 ns" { add~93COUT1_104 add~96 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.607 ns) 2.722 ns cnt\[4\]~reg0 7 REG LAB_X1_Y24 5 " "Info: 7: + IC(0.222 ns) + CELL(0.607 ns) = 2.722 ns; Loc. = LAB_X1_Y24; Fanout = 5; REG Node = 'cnt\[4\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "0.829 ns" { add~96 cnt[4]~reg0 } "NODE_NAME" } "" } } { "count24_04.vhd" "" { Text "e:/tangdaiweneda/count24_04/count24_04.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.030 ns ( 74.58 % ) " "Info: Total cell delay = 2.030 ns ( 74.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.692 ns ( 25.42 % ) " "Info: Total interconnect delay = 0.692 ns ( 25.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count24_04" "UNKNOWN" "V1" "e:/tangdaiweneda/count24_04/db/count24_04.quartus_db" { Floorplan "e:/tangdaiweneda/count24_04/" "" "2.722 ns" { cnt[0]~reg0 add~78COUT1_102 add~83COUT1 add~88COUT1_103 add~93COUT1_104 add~96 cnt[4]~reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 05 09:09:51 2008 " "Info: Processing ended: Mon May 05 09:09:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}