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📄 count24_04.map.eqn

📁 24进制倒计时 24进制倒计时用VHDL编写
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L25Q is y~reg0
--operation mode is normal

A1L25Q_lut_out = clr & A1L22Q & A1L23 # !clr & (A1L25Q);
A1L25Q = DFFEAS(A1L25Q_lut_out, clk, VCC, , , , , , );


--A1L14Q is cnt[0]~reg0
--operation mode is normal

A1L14Q_lut_out = A1L1;
A1L14Q = DFFEAS(A1L14Q_lut_out, clk, clr, , , , , , );


--A1L16Q is cnt[1]~reg0
--operation mode is normal

A1L16Q_lut_out = A1L3;
A1L16Q = DFFEAS(A1L16Q_lut_out, clk, clr, , , , , , );


--A1L18Q is cnt[2]~reg0
--operation mode is normal

A1L18Q_lut_out = A1L5;
A1L18Q = DFFEAS(A1L18Q_lut_out, clk, clr, , , , , , );


--A1L20Q is cnt[3]~reg0
--operation mode is normal

A1L20Q_lut_out = A1L7 $ (A1L22Q & A1L23);
A1L20Q = DFFEAS(A1L20Q_lut_out, clk, clr, , , , , , );


--A1L22Q is cnt[4]~reg0
--operation mode is normal

A1L22Q_lut_out = A1L9 $ (A1L22Q & A1L23);
A1L22Q = DFFEAS(A1L22Q_lut_out, clk, clr, , , , , , );


--A1L23 is rtl~30
--operation mode is normal

A1L23 = A1L14Q & A1L16Q & A1L18Q & !A1L20Q;


--A1L1 is add~76
--operation mode is arithmetic

A1L1 = !A1L14Q;

--A1L2 is add~78
--operation mode is arithmetic

A1L2 = CARRY(A1L14Q);


--A1L3 is add~81
--operation mode is arithmetic

A1L3_carry_eqn = A1L2;
A1L3 = A1L16Q $ (A1L3_carry_eqn);

--A1L4 is add~83
--operation mode is arithmetic

A1L4 = CARRY(!A1L2 # !A1L16Q);


--A1L5 is add~86
--operation mode is arithmetic

A1L5_carry_eqn = A1L4;
A1L5 = A1L18Q $ (!A1L5_carry_eqn);

--A1L6 is add~88
--operation mode is arithmetic

A1L6 = CARRY(A1L18Q & (!A1L4));


--A1L7 is add~91
--operation mode is arithmetic

A1L7_carry_eqn = A1L6;
A1L7 = A1L20Q $ (A1L7_carry_eqn);

--A1L8 is add~93
--operation mode is arithmetic

A1L8 = CARRY(!A1L6 # !A1L20Q);


--A1L9 is add~96
--operation mode is normal

A1L9_carry_eqn = A1L8;
A1L9 = A1L22Q $ (!A1L9_carry_eqn);


--clr is clr
--operation mode is input

clr = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--y is y
--operation mode is output

y = OUTPUT(A1L25Q);


--cnt[0] is cnt[0]
--operation mode is output

cnt[0] = OUTPUT(A1L14Q);


--cnt[1] is cnt[1]
--operation mode is output

cnt[1] = OUTPUT(A1L16Q);


--cnt[2] is cnt[2]
--operation mode is output

cnt[2] = OUTPUT(A1L18Q);


--cnt[3] is cnt[3]
--operation mode is output

cnt[3] = OUTPUT(A1L20Q);


--cnt[4] is cnt[4]
--operation mode is output

cnt[4] = OUTPUT(A1L22Q);


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