count24_04.fit.eqn

24进制倒计时 24进制倒计时用VHDL编写

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L29Q is y~reg0 at LC_X2_Y24_N3
--operation mode is normal

A1L29Q_lut_out = clr & A1L27 & A1L26Q # !clr & (A1L29Q);
A1L29Q = DFFEAS(A1L29Q_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L20Q is cnt[1]~reg0 at LC_X1_Y24_N4
--operation mode is normal

A1L20Q_lut_out = A1L4;
A1L20Q = DFFEAS(A1L20Q_lut_out, GLOBAL(clk), GLOBAL(clr), , , , , , );


--A1L22Q is cnt[2]~reg0 at LC_X1_Y24_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L22Q_lut_out = GND;
A1L22Q = DFFEAS(A1L22Q_lut_out, GLOBAL(clk), GLOBAL(clr), , , A1L7, , , VCC);


--A1L24Q is cnt[3]~reg0 at LC_X1_Y24_N3
--operation mode is normal

A1L24Q_lut_out = A1L10 $ (A1L26Q & A1L27);
A1L24Q = DFFEAS(A1L24Q_lut_out, GLOBAL(clk), GLOBAL(clr), , , , , , );


--A1L26Q is cnt[4]~reg0 at LC_X1_Y24_N2
--operation mode is normal

A1L26Q_lut_out = A1L13 $ (A1L26Q & A1L27);
A1L26Q = DFFEAS(A1L26Q_lut_out, GLOBAL(clk), GLOBAL(clr), , , , , , );


--A1L27 is rtl~30 at LC_X1_Y24_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L18Q_qfbk = A1L18Q;
A1L27 = !A1L24Q & A1L20Q & A1L18Q_qfbk & A1L22Q;

--A1L18Q is cnt[0]~reg0 at LC_X1_Y24_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L18Q = DFFEAS(A1L27, GLOBAL(clk), GLOBAL(clr), , , A1L1, , , VCC);


--A1L1 is add~76 at LC_X1_Y24_N5
--operation mode is arithmetic

A1L1 = !A1L18Q;

--A1L2 is add~78 at LC_X1_Y24_N5
--operation mode is arithmetic

A1L2_cout_0 = A1L18Q;
A1L2 = CARRY(A1L2_cout_0);

--A1L3 is add~78COUT1_102 at LC_X1_Y24_N5
--operation mode is arithmetic

A1L3_cout_1 = A1L18Q;
A1L3 = CARRY(A1L3_cout_1);


--A1L4 is add~81 at LC_X1_Y24_N6
--operation mode is arithmetic

A1L4 = A1L20Q $ A1L2;

--A1L5 is add~83 at LC_X1_Y24_N6
--operation mode is arithmetic

A1L5_cout_0 = !A1L2 # !A1L20Q;
A1L5 = CARRY(A1L5_cout_0);

--A1L6 is add~83COUT1 at LC_X1_Y24_N6
--operation mode is arithmetic

A1L6_cout_1 = !A1L3 # !A1L20Q;
A1L6 = CARRY(A1L6_cout_1);


--A1L7 is add~86 at LC_X1_Y24_N7
--operation mode is arithmetic

A1L7 = A1L22Q $ !A1L5;

--A1L8 is add~88 at LC_X1_Y24_N7
--operation mode is arithmetic

A1L8_cout_0 = A1L22Q & !A1L5;
A1L8 = CARRY(A1L8_cout_0);

--A1L9 is add~88COUT1_103 at LC_X1_Y24_N7
--operation mode is arithmetic

A1L9_cout_1 = A1L22Q & !A1L6;
A1L9 = CARRY(A1L9_cout_1);


--A1L10 is add~91 at LC_X1_Y24_N8
--operation mode is arithmetic

A1L10 = A1L24Q $ A1L8;

--A1L11 is add~93 at LC_X1_Y24_N8
--operation mode is arithmetic

A1L11_cout_0 = !A1L8 # !A1L24Q;
A1L11 = CARRY(A1L11_cout_0);

--A1L12 is add~93COUT1_104 at LC_X1_Y24_N8
--operation mode is arithmetic

A1L12_cout_1 = !A1L9 # !A1L24Q;
A1L12 = CARRY(A1L12_cout_1);


--A1L13 is add~96 at LC_X1_Y24_N9
--operation mode is normal

A1L13 = A1L26Q $ (!A1L11);


--clr is clr at PIN_7
--operation mode is input

clr = INPUT();


--clk is clk at PIN_28
--operation mode is input

clk = INPUT();


--y is y at PIN_11
--operation mode is output

y = OUTPUT(A1L29Q);


--cnt[0] is cnt[0] at PIN_3
--operation mode is output

cnt[0] = OUTPUT(A1L18Q);


--cnt[1] is cnt[1] at PIN_4
--operation mode is output

cnt[1] = OUTPUT(A1L20Q);


--cnt[2] is cnt[2] at PIN_5
--operation mode is output

cnt[2] = OUTPUT(A1L22Q);


--cnt[3] is cnt[3] at PIN_6
--operation mode is output

cnt[3] = OUTPUT(A1L24Q);


--cnt[4] is cnt[4] at PIN_8
--operation mode is output

cnt[4] = OUTPUT(A1L26Q);