count24_04.vhd

24进制倒计时 24进制倒计时用VHDL编写

library ieee;
use ieee.std_logic_1164.all;
entity count24_04 is
port ( clr : in std_logic;
       clk : in std_logic;
       y: out std_logic;
       cnt : buffer integer range 23 downto 0);
end count24_04;
architecture example5 of count24_04 is
begin
  process(clr,clk)
   begin
     if clr='0' then cnt<=0;
     elsif clk'event and clk='1' then
       if(cnt=23) then
         cnt<=0;
         y<='1';
       else
         cnt<=cnt+1;
         y<='0';
       end if;
     end if;
   end process;
end example5;