gei_lei.map.qmsg

格雷编码 格雷编码用VHDL编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 17 15:07:44 2008 " "Info: Processing started: Thu Apr 17 15:07:44 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gei_lei -c gei_lei " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gei_lei -c gei_lei" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gei_lei.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gei_lei.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gei_lei-example3 " "Info: Found design unit 1: gei_lei-example3" {  } { { "gei_lei.vhd" "" { Text "E:/tangdaiweneda/gei_lei/gei_lei.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 gei_lei " "Info: Found entity 1: gei_lei" {  } { { "gei_lei.vhd" "" { Text "E:/tangdaiweneda/gei_lei/gei_lei.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "gei_lei " "Info: Elaborating entity \"gei_lei\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s gei_lei.vhd(13) " "Warning (10492): VHDL Process Statement warning at gei_lei.vhd(13): signal \"s\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "gei_lei.vhd" "" { Text "E:/tangdaiweneda/gei_lei/gei_lei.vhd" 13 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "y\[0\]~3 " "Warning: Node \"y\[0\]~3\"" {  } { { "gei_lei.vhd" "" { Text "E:/tangdaiweneda/gei_lei/gei_lei.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "y\[1\]~4 " "Warning: Node \"y\[1\]~4\"" {  } { { "gei_lei.vhd" "" { Text "E:/tangdaiweneda/gei_lei/gei_lei.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "y\[2\]~5 " "Warning: Node \"y\[2\]~5\"" {  } { { "gei_lei.vhd" "" { Text "E:/tangdaiweneda/gei_lei/gei_lei.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } {  } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "8 " "Info: Implemented 8 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "0 " "Info: Implemented 0 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "3 " "Info: Implemented 3 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 17 15:07:46 2008 " "Info: Processing ended: Thu Apr 17 15:07:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}