gei_lei.fit.eqn

格雷编码 格雷编码用VHDL编写

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--A1L4 is Mux~20 at LC_X1_Y24_N5
--operation mode is normal

A1L4 = c3 $ c2;


--A1L5 is Mux~21 at LC_X1_Y24_N2
--operation mode is normal

A1L5 = c1 $ c2;


--c2 is c2 at PIN_3
--operation mode is input

c2 = INPUT();


--c3 is c3 at PIN_4
--operation mode is input

c3 = INPUT();


--c1 is c1 at PIN_2
--operation mode is input

c1 = INPUT();


--y[0] is y[0] at PIN_6
--operation mode is bidir

y[0]_tri_out = TRI(A1L4, VCC);
y[0] = BIDIR(y[0]_tri_out);


--y[1] is y[1] at PIN_7
--operation mode is bidir

y[1]_tri_out = TRI(A1L5, VCC);
y[1] = BIDIR(y[1]_tri_out);


--y[2] is y[2] at PIN_8
--operation mode is bidir

y[2]_tri_out = TRI(c1, VCC);
y[2] = BIDIR(y[2]_tri_out);