gei_lei.map.eqn

来自「格雷编码 格雷编码用VHDL编写」· EQN 代码 · 共 65 行

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--A1L4 is Mux~20
--operation mode is normal

A1L4 = c2 $ c3;


--A1L5 is Mux~21
--operation mode is normal

A1L5 = c2 $ c1;


--c2 is c2
--operation mode is input

c2 = INPUT();


--c3 is c3
--operation mode is input

c3 = INPUT();


--c1 is c1
--operation mode is input

c1 = INPUT();


--y[0] is y[0]
--operation mode is bidir

y[0]_tri_out = TRI(A1L4, VCC);
y[0] = BIDIR(y[0]_tri_out);


--y[1] is y[1]
--operation mode is bidir

y[1]_tri_out = TRI(A1L5, VCC);
y[1] = BIDIR(y[1]_tri_out);


--y[2] is y[2]
--operation mode is bidir

y[2]_tri_out = TRI(c1, VCC);
y[2] = BIDIR(y[2]_tri_out);