gei_lei.vhd

来自「格雷编码 格雷编码用VHDL编写」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
entity gei_lei is
port (c1,c2,c3: in std_logic;
      y: inout std_logic_vector(2 downto 0));
end gei_lei; 
architecture example3 of gei_lei is
signal s: std_logic_vector(2 downto 0);
 begin 
    s<=c1&c2&c3;
    process(c1,c2,c3)
     begin
      case s is
        when "000"=>y<="000";
        when "001"=>y<="001";
        when "010"=>y<="011";
        when "011"=>y<="010";
        when "100"=>y<="110";
        when "101"=>y<="111";
        when "110"=>y<="101";
        when "111"=>y<="100";
     end case;
   end process;
end example3;