gei_lei.fit.rpt

格雷编码 格雷编码用VHDL编写

; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/tangdaiweneda/gei_lei/gei_lei.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/tangdaiweneda/gei_lei/gei_lei.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 2 / 12,060 ( < 1 % ) ;
;     -- Combinational with no register       ; 2                    ;
;     -- Register only                        ; 0                    ;
;     -- Combinational with a register        ; 0                    ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 0                    ;
;     -- 3 input functions                    ; 0                    ;
;     -- 2 input functions                    ; 2                    ;
;     -- 1 input functions                    ; 0                    ;
;     -- 0 input functions                    ; 0                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 2                    ;
;     -- arithmetic mode                      ; 0                    ;
;     -- qfbk mode                            ; 0                    ;
;     -- register cascade mode                ; 0                    ;
;     -- synchronous clear/load mode          ; 0                    ;
;     -- asynchronous clear/load mode         ; 0                    ;
;                                             ;                      ;
; Total LABs                                  ; 1 / 1,206 ( < 1 % )  ;
; Logic elements in carry chains              ; 0                    ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 6 / 173 ( 3 % )      ;
;     -- Clock pins                           ; 0 / 2 ( 0 % )        ;
; Global signals                              ; 0                    ;
; M4Ks                                        ; 0 / 52 ( 0 % )       ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )  ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )  ;
; PLLs                                        ; 0 / 2 ( 0 % )        ;
; Global clocks                               ; 0 / 8 ( 0 % )        ;
; Maximum fan-out node                        ; c2                   ;
; Maximum fan-out                             ; 2                    ;
; Highest non-global fan-out signal           ; c2                   ;
; Highest non-global fan-out                  ; 2                    ;
; Total fan-out                               ; 7                    ;
; Average fan-out                             ; 0.70                 ;
+---------------------------------------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; c1   ; 2     ; 1        ; 0            ; 26           ; 1           ; 2                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; c2   ; 3     ; 1        ; 0            ; 25           ; 0           ; 2                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; c3   ; 4     ; 1        ; 0            ; 25           ; 1           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins                                                                                                                                                                                                                                                                                                                                                           ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load        ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; y[0] ; 6     ; 1        ; 0            ; 24           ; 0           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; Unspecified ;
; y[1] ; 7     ; 1        ; 0            ; 24           ; 1           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; Unspecified ;
; y[2] ; 8     ; 1        ; 0            ; 24           ; 2           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; Unspecified ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+


+-----------------------------------------------------------+
; I/O Bank Usage                                            ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;