wr_fifo.tan.qmsg

S11_USB ,maxII 的FPGA芯片

{ "Info" "ITDB_TH_RESULT" "STATE.WRITE u_flagb clk 2.088 ns register " "Info: th for register \"STATE.WRITE\" (data pin = \"u_flagb\", clock pin = \"clk\") is 2.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.204 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.204 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { clk } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.935 ns) 3.991 ns u_ifclk~reg0 2 REG LC_X19_Y10_N2 20 " "Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 20; REG Node = 'u_ifclk~reg0'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "2.522 ns" { clk u_ifclk~reg0 } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 110 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.502 ns) + CELL(0.711 ns) 9.204 ns STATE.WRITE 3 REG LC_X4_Y1_N8 2 " "Info: 3: + IC(4.502 ns) + CELL(0.711 ns) = 9.204 ns; Loc. = LC_X4_Y1_N8; Fanout = 2; REG Node = 'STATE.WRITE'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "5.213 ns" { u_ifclk~reg0 STATE.WRITE } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 33.84 % " "Info: Total cell delay = 3.115 ns ( 33.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.089 ns 66.16 % " "Info: Total interconnect delay = 6.089 ns ( 66.16 % )" {  } {  } 0}  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "9.204 ns" { clk u_ifclk~reg0 STATE.WRITE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.204 ns" { clk clk~out0 u_ifclk~reg0 STATE.WRITE } { 0.000ns 0.000ns 1.587ns 4.502ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.131 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns u_flagb 1 PIN PIN_54 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_54; Fanout = 5; PIN Node = 'u_flagb'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { u_flagb } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.353 ns) + CELL(0.309 ns) 7.131 ns STATE.WRITE 2 REG LC_X4_Y1_N8 2 " "Info: 2: + IC(5.353 ns) + CELL(0.309 ns) = 7.131 ns; Loc. = LC_X4_Y1_N8; Fanout = 2; REG Node = 'STATE.WRITE'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "5.662 ns" { u_flagb STATE.WRITE } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 24.93 % " "Info: Total cell delay = 1.778 ns ( 24.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.353 ns 75.07 % " "Info: Total interconnect delay = 5.353 ns ( 75.07 % )" {  } {  } 0}  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "7.131 ns" { u_flagb STATE.WRITE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.131 ns" { u_flagb u_flagb~out0 STATE.WRITE } { 0.000ns 0.000ns 5.353ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "9.204 ns" { clk u_ifclk~reg0 STATE.WRITE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.204 ns" { clk clk~out0 u_ifclk~reg0 STATE.WRITE } { 0.000ns 0.000ns 1.587ns 4.502ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "7.131 ns" { u_flagb STATE.WRITE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.131 ns" { u_flagb u_flagb~out0 STATE.WRITE } { 0.000ns 0.000ns 5.353ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk u_ifclk u_ifclk~reg0 9.863 ns register " "Info: Minimum tco from clock \"clk\" to destination pin \"u_ifclk\" through register \"u_ifclk~reg0\" is 9.863 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.767 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to source register is 3.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { clk } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.711 ns) 3.767 ns u_ifclk~reg0 2 REG LC_X19_Y10_N2 20 " "Info: 2: + IC(1.587 ns) + CELL(0.711 ns) = 3.767 ns; Loc. = LC_X19_Y10_N2; Fanout = 20; REG Node = 'u_ifclk~reg0'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "2.298 ns" { clk u_ifclk~reg0 } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 110 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 57.87 % " "Info: Total cell delay = 2.180 ns ( 57.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.587 ns 42.13 % " "Info: Total interconnect delay = 1.587 ns ( 42.13 % )" {  } {  } 0}  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "3.767 ns" { clk u_ifclk~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.767 ns" { clk clk~out0 u_ifclk~reg0 } { 0.0ns 0.0ns 1.587ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 110 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.872 ns + Shortest register pin " "Info: + Shortest register to pin delay is 5.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns u_ifclk~reg0 1 REG LC_X19_Y10_N2 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y10_N2; Fanout = 20; REG Node = 'u_ifclk~reg0'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { u_ifclk~reg0 } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 110 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.748 ns) + CELL(2.124 ns) 5.872 ns u_ifclk 2 PIN PIN_50 0 " "Info: 2: + IC(3.748 ns) + CELL(2.124 ns) = 5.872 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'u_ifclk'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "5.872 ns" { u_ifclk~reg0 u_ifclk } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 36.17 % " "Info: Total cell delay = 2.124 ns ( 36.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.748 ns 63.83 % " "Info: Total interconnect delay = 3.748 ns ( 63.83 % )" {  } {  } 0}  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "5.872 ns" { u_ifclk~reg0 u_ifclk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.872 ns" { u_ifclk~reg0 u_ifclk } { 0.0ns 3.748ns } { 0.0ns 2.124ns } } }  } 0}  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "3.767 ns" { clk u_ifclk~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.767 ns" { clk clk~out0 u_ifclk~reg0 } { 0.0ns 0.0ns 1.587ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "5.872 ns" { u_ifclk~reg0 u_ifclk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.872 ns" { u_ifclk~reg0 u_ifclk } { 0.0ns 3.748ns } { 0.0ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 18 16:52:58 2006 " "Info: Processing ended: Tue Apr 18 16:52:58 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}