wr_fifo.map.qmsg

S11_USB ,maxII 的FPGA芯片

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 18 16:52:48 2006 " "Info: Processing started: Tue Apr 18 16:52:48 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off wr_fifo -c wr_fifo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off wr_fifo -c wr_fifo" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "wr_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file wr_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 wr_fifo " "Info: Found entity 1: wr_fifo" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "wr_fifo " "Info: Elaborating entity \"wr_fifo\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 wr_fifo.v(65) " "Warning: Verilog HDL assignment warning at wr_fifo.v(65): truncated value with size 32 to match size of target (16)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wr_fifo.v(66) " "Warning: Verilog HDL assignment warning at wr_fifo.v(66): truncated value with size 32 to match size of target (1)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wr_fifo.v(67) " "Warning: Verilog HDL assignment warning at wr_fifo.v(67): truncated value with size 32 to match size of target (1)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wr_fifo.v(68) " "Warning: Verilog HDL assignment warning at wr_fifo.v(68): truncated value with size 32 to match size of target (1)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 68 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wr_fifo.v(83) " "Warning: Verilog HDL assignment warning at wr_fifo.v(83): truncated value with size 32 to match size of target (1)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 83 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 wr_fifo.v(84) " "Warning: Verilog HDL assignment warning at wr_fifo.v(84): truncated value with size 32 to match size of target (16)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wr_fifo.v(89) " "Warning: Verilog HDL assignment warning at wr_fifo.v(89): truncated value with size 32 to match size of target (1)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 89 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wr_fifo.v(101) " "Warning: Verilog HDL assignment warning at wr_fifo.v(101): truncated value with size 32 to match size of target (1)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wr_fifo.v(102) " "Warning: Verilog HDL assignment warning at wr_fifo.v(102): truncated value with size 32 to match size of target (1)" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 102 0 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "u_slrd~reg0 High " "Info: Power-up level of register \"u_slrd~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 35 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "u_slrd~reg0 data_in VCC " "Warning: Reduced register \"u_slrd~reg0\" with stuck data_in port to stuck value VCC" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 35 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "u_sloe~reg0 High " "Info: Power-up level of register \"u_sloe~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 36 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "u_sloe~reg0 data_in VCC " "Warning: Reduced register \"u_sloe~reg0\" with stuck data_in port to stuck value VCC" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 36 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|wr_fifo\|STATE 2 0 " "Info: State machine \"\|wr_fifo\|STATE\" contains 2 states and 0 state bits" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 55 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|wr_fifo\|STATE " "Info: Selected Auto state machine encoding method for state machine \"\|wr_fifo\|STATE\"" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 55 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|wr_fifo\|STATE " "Info: Encoding result for state machine \"\|wr_fifo\|STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "1 " "Info: Completed encoding using 1 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.WRITE " "Info: Encoded state bit \"STATE.WRITE\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|wr_fifo\|STATE.IDLE 0 " "Info: State \"\|wr_fifo\|STATE.IDLE\" uses code string \"0\"" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 55 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|wr_fifo\|STATE.WRITE 1 " "Info: State \"\|wr_fifo\|STATE.WRITE\" uses code string \"1\"" {  } {  } 0}  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 55 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "u_slrd VCC " "Warning: Pin \"u_slrd\" stuck at VCC" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 35 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "u_sloe VCC " "Warning: Pin \"u_sloe\" stuck at VCC" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 36 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "u_addr0 GND " "Warning: Pin \"u_addr0\" stuck at GND" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 39 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "u_addr1 VCC " "Warning: Pin \"u_addr1\" stuck at VCC" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 40 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "45 " "Info: Implemented 45 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "22 " "Info: Implemented 22 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "20 " "Info: Implemented 20 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 18 16:52:49 2006 " "Info: Processing ended: Tue Apr 18 16:52:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}