wr_fifo.fit.qmsg

S11_USB ,maxII 的FPGA芯片

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 18 16:52:51 2006 " "Info: Processing started: Tue Apr 18 16:52:51 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off wr_fifo -c wr_fifo " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off wr_fifo -c wr_fifo" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "wr_fifo EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"wr_fifo\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "u_ifclk~reg0 Global clock " "Info: Automatically promoted some destinations of signal \"u_ifclk~reg0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "u_ifclk " "Info: Destination \"u_ifclk\" may be non-global or may not use global clock" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 33 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "u_ifclk~reg0 " "Info: Destination \"u_ifclk~reg0\" may be non-global or may not use global clock" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 110 -1 0 } }  } 0}  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 110 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.750 ns register register " "Info: Estimated most critical path is register to register delay of 2.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATE.WRITE 1 REG LAB_X4_Y1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y1; Fanout = 2; REG Node = 'STATE.WRITE'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { STATE.WRITE } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.590 ns) 0.740 ns u_slwr~23 2 COMB LAB_X4_Y1 17 " "Info: 2: + IC(0.150 ns) + CELL(0.590 ns) = 0.740 ns; Loc. = LAB_X4_Y1; Fanout = 17; COMB Node = 'u_slwr~23'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "0.740 ns" { STATE.WRITE u_slwr~23 } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.143 ns) + CELL(0.867 ns) 2.750 ns data_out\[0\]~reg0 3 REG LAB_X4_Y2 4 " "Info: 3: + IC(1.143 ns) + CELL(0.867 ns) = 2.750 ns; Loc. = LAB_X4_Y2; Fanout = 4; REG Node = 'data_out\[0\]~reg0'" {  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "2.010 ns" { u_slwr~23 data_out[0]~reg0 } "NODE_NAME" } "" } } { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 97 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 52.98 % " "Info: Total cell delay = 1.457 ns ( 52.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.293 ns 47.02 % " "Info: Total interconnect delay = 1.293 ns ( 47.02 % )" {  } {  } 0}  } { { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "2.750 ns" { STATE.WRITE u_slwr~23 data_out[0]~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: The following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "u_slrd VCC " "Info: Pin u_slrd has VCC driving its datain port" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 35 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "u_slrd" } } } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { u_slrd } "NODE_NAME" } "" } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" "" { u_slrd } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "u_sloe VCC " "Info: Pin u_sloe has VCC driving its datain port" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 36 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "u_sloe" } } } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { u_sloe } "NODE_NAME" } "" } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" "" { u_sloe } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "u_addr0 GND " "Info: Pin u_addr0 has GND driving its datain port" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 39 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "u_addr0" } } } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { u_addr0 } "NODE_NAME" } "" } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" "" { u_addr0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "u_addr1 VCC " "Info: Pin u_addr1 has VCC driving its datain port" {  } { { "wr_fifo.v" "" { Text "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.v" 40 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "u_addr1" } } } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" "" { Report "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo_cmp.qrpt" Compiler "wr_fifo" "UNKNOWN" "V1" "E:/68013_code/дFIFO/дFIFO/wr_fifo/db/wr_fifo.quartus_db" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/" "" "" { u_addr1 } "NODE_NAME" } "" } } { "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" { Floorplan "E:/68013_code/дFIFO/дFIFO/wr_fifo/wr_fifo.fld" "" "" { u_addr1 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 18 16:52:54 2006 " "Info: Processing ended: Tue Apr 18 16:52:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}