asyn_rd.tan.qmsg

S11_USB ,maxII 的FPGA芯片

{ "Info" "ITDB_FULL_TPD_RESULT" "u_flagc u_flagc_led 11.542 ns Longest " "Info: Longest tpd from source pin \"u_flagc\" to destination pin \"u_flagc_led\" is 11.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns u_flagc 1 PIN PIN_AA15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AA15; Fanout = 3; PIN Node = 'u_flagc'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "" { u_flagc } "NODE_NAME" } "" } } { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.521 ns) + CELL(3.087 ns) 11.542 ns u_flagc_led 2 PIN PIN_A11 0 " "Info: 2: + IC(7.521 ns) + CELL(3.087 ns) = 11.542 ns; Loc. = PIN_A11; Fanout = 0; PIN Node = 'u_flagc_led'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "10.608 ns" { u_flagc u_flagc_led } "NODE_NAME" } "" } } { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.021 ns 34.84 % " "Info: Total cell delay = 4.021 ns ( 34.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.521 ns 65.16 % " "Info: Total interconnect delay = 7.521 ns ( 65.16 % )" {  } {  } 0}  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "11.542 ns" { u_flagc u_flagc_led } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.542 ns" { u_flagc u_flagc~combout u_flagc_led } { 0.000ns 0.000ns 7.521ns } { 0.000ns 0.934ns 3.087ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] altera_internal_jtag altera_internal_jtag~TCKUTAP 1.650 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.650 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.759 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } {