asyn_rd.tan.qmsg

S11_USB ,maxII 的FPGA芯片

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 30 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "u_ifclk~reg0 " "Info: Detected ripple clock \"u_ifclk~reg0\" as buffer" {  } { { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 98 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "u_ifclk~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|match_out register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 131.98 MHz 7.577 ns Internal " "Info: Clock \"clk\" has Internal fmax of 131.98 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|match_out\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena\" (period= 7.577 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.297 ns + Longest register register " "Info: + Longest register to register delay is 7.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|match_out 1 REG LCFF_X30_Y3_N11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y3_N11; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|match_out'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } "NODE_NAME" } "" } } { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 289 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.664 ns) 1.124 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~444 2 COMB LCCOMB_X30_Y3_N22 1 " "Info: 2: + IC(0.460 ns) + CELL(0.664 ns) = 1.124 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~444'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.124 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~444 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.464 ns) + CELL(0.378 ns) 2.966 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~446 3 COMB LCCOMB_X27_Y7_N2 1 " "Info: 3: + IC(1.464 ns) + CELL(0.378 ns) = 2.966 ns; Loc. = LCCOMB_X27_Y7_N2; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~446'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.842 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~444 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~446 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.636 ns) 3.987 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~450 4 COMB LCCOMB_X27_Y7_N18 2 " "Info: 4: + IC(0.385 ns) + CELL(0.636 ns) = 3.987 ns; Loc. = LCCOMB_X27_Y7_N18; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~450'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.021 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~446 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~450 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.636 ns) 5.007 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~452 5 COMB LCCOMB_X27_Y7_N20 5 " "Info: 5: + IC(0.384 ns) + CELL(0.636 ns) = 5.007 ns; Loc. = LCCOMB_X27_Y7_N20; Fanout = 5; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~452'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.020 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~450 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~452 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.636 ns) 7.187 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena~85 6 COMB LCCOMB_X29_Y5_N24 1 " "Info: 6: + IC(1.544 ns) + CELL(0.636 ns) = 7.187 ns; Loc. = LCCOMB_X29_Y5_N24; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena~85'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "2.180 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~452 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~85 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 7.297 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 7 REG LCFF_X29_Y5_N25 3 " "Info: 7: + IC(0.000 ns) + CELL(0.110 ns) = 7.297 ns; Loc. = LCFF_X29_Y5_N25; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "0.110 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~85 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.060 ns 41.94 % " "Info: Total cell delay = 3.060 ns ( 41.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.237 ns 58.06 % " "Info: Total interconnect delay = 4.237 ns ( 58.06 % )" {  } {  } 0}  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "7.297 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~444 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~446 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~450 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~452 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~85 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.297 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~444 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~446 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~450 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~452 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~85 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.460ns 1.464ns 0.385ns 0.384ns 1.544ns 0.000ns } { 0.000ns 0.664ns 0.378ns 0.636ns 0.636ns 0.636ns 0.110ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.010 ns - Smallest " "Info: - Smallest clock skew is -0.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.966 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.966 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "" { clk } "NODE_NAME" } "" } } { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns clk~clkctrl 2 COMB CLKCTRL_G14 430 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 430; COMB Node = 'clk~clkctrl'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "0.117 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.679 ns) 2.966 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 3 REG LCFF_X29_Y5_N25 3 " "Info: 3: + IC(1.070 ns) + CELL(0.679 ns) = 2.966 ns; Loc. = LCFF_X29_Y5_N25; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.749 ns" { clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 59.98 % " "Info: Total cell delay = 1.779 ns ( 59.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.187 ns 40.02 % " "Info: Total interconnect delay = 1.187 ns ( 40.02 % )" {  } {  } 0}  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "2.966 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.966 ns" { clk clk~combout clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.117ns 1.070ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.976 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.976 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "" { clk } "NODE_NAME" } "" } } { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns clk~clkctrl 2 COMB CLKCTRL_G14 430 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 430; COMB Node = 'clk~clkctrl'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "0.117 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.679 ns) 2.976 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|match_out 3 REG LCFF_X30_Y3_N11 1 " "Info: 3: + IC(1.080 ns) + CELL(0.679 ns) = 2.976 ns; Loc. = LCFF_X30_Y3_N11; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|match_out'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.759 ns" { clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } "NODE_NAME" } "" } } { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 289 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 59.78 % " "Info: Total cell delay = 1.779 ns ( 59.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.197 ns 40.22 % " "Info: Total interconnect delay = 1.197 ns ( 40.22 % )" {  } {  } 0}  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "2.976 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.976 ns" { clk clk~combout clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } { 0.000ns 0.000ns 0.117ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "2.966 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.966 ns" { clk clk~combout clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.117ns 1.070ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "2.976 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.976 ns" { clk clk~combout clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } { 0.000ns 0.000ns 0.117ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 289 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0}  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "7.297 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~444 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~446 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~450 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~452 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~85 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.297 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~444 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~446 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~450 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~452 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~85 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.460ns 1.464ns 0.385ns 0.384ns 1.544ns 0.000ns } { 0.000ns 0.664ns 0.378ns 0.636ns 0.636ns 0.636ns 0.110ns } } } { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "2.966 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.966 ns" { clk clk~combout clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.117ns 1.070ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "2.976 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.976 ns" { clk clk~combout clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|match_out } { 0.000ns 0.000ns 0.117ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}