asyn_rd.fit.qmsg

S11_USB ,maxII 的FPGA芯片

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 4 33 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  33 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 1 42 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 3 37 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 3 total pin(s) used --  37 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 39 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.30V 4 32 " "Info: I/O bank number 6 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  32 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.30V 20 20 " "Info: I/O bank number 7 does not use VREF pins and has 3.30V VCCIO pins. 20 total pin(s) used --  20 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 1 42 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.123 ns register register " "Info: Estimated most critical path is register to register delay of 4.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LAB_X25_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y7; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.976 ns) + CELL(0.664 ns) 1.640 ns sld_hub:sld_hub_inst\|hub_tdo~245 2 COMB LAB_X26_Y9 1 " "Info: 2: + IC(0.976 ns) + CELL(0.664 ns) = 1.640 ns; Loc. = LAB_X26_Y9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~245'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.640 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~245 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.378 ns) 3.197 ns sld_hub:sld_hub_inst\|hub_tdo~246 3 COMB LAB_X26_Y8 1 " "Info: 3: + IC(1.179 ns) + CELL(0.378 ns) = 3.197 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~246'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "1.557 ns" { sld_hub:sld_hub_inst|hub_tdo~245 sld_hub:sld_hub_inst|hub_tdo~246 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.152 ns) + CELL(0.664 ns) 4.013 ns sld_hub:sld_hub_inst\|hub_tdo~250 4 COMB LAB_X26_Y8 1 " "Info: 4: + IC(0.152 ns) + CELL(0.664 ns) = 4.013 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~250'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "0.816 ns" { sld_hub:sld_hub_inst|hub_tdo~246 sld_hub:sld_hub_inst|hub_tdo~250 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 4.123 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LAB_X26_Y8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 4.123 ns; Loc. = LAB_X26_Y8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "0.110 ns" { sld_hub:sld_hub_inst|hub_tdo~250 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns 44.05 % " "Info: Total cell delay = 1.816 ns ( 44.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.307 ns 55.95 % " "Info: Total interconnect delay = 2.307 ns ( 55.95 % )" {  } {  } 0}  } { { "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" "" { Report "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd_cmp.qrpt" Compiler "asyn_rd" "UNKNOWN" "V1" "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/db/asyn_rd.quartus_db" { Floorplan "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/" "" "4.123 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~245 sld_hub:sld_hub_inst|hub_tdo~246 sld_hub:sld_hub_inst|hub_tdo~250 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}