asyn_rd.map.qmsg

S11_USB ,maxII 的FPGA芯片

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 05 15:26:40 2006 " "Info: Processing started: Tue Dec 05 15:26:40 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off asyn_rd -c asyn_rd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off asyn_rd -c asyn_rd" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "asyn_rd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file asyn_rd.v" { { "Info" "ISGN_ENTITY_NAME" "1 asyn_rd " "Info: Found entity 1: asyn_rd" {  } { { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "asyn_rd " "Info: Elaborating entity \"asyn_rd\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asyn_rd.v(63) " "Warning: Verilog HDL assignment warning at asyn_rd.v(63): truncated value with size 32 to match size of target (1)" {  } { { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asyn_rd.v(64) " "Warning: Verilog HDL assignment warning at asyn_rd.v(64): truncated value with size 32 to match size of target (1)" {  } { { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 64 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asyn_rd.v(86) " "Warning: Verilog HDL assignment warning at asyn_rd.v(86): truncated value with size 32 to match size of target (1)" {  } { { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asyn_rd.v(87) " "Warning: Verilog HDL assignment warning at asyn_rd.v(87): truncated value with size 32 to match size of target (1)" {  } { { "asyn_rd.v" "" { Text "E:/code/EP2C20/T1_USB/READ_FIFO/rd_fifo/asyn_rd.v" 87 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 170 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0}  } {  } 0}