uart_if.vo

S7_UART串口输出

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "12/05/2006 17:36:22"

// 
// Device: Altera EP2C20F484C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

`timescale 1 ps/ 1 ps

module 	uart_if_rom (
	rst_n,
	MCLK,
	rxd,
	txd);
input 	rst_n;
input 	MCLK;
input 	rxd;
output 	txd;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("uart_if_v.sdo");
// synopsys translate_on

wire \inst4|acc[12] ;
wire \inst5|U1|u2|clkdiv_5_sum3_a ;
wire \inst3|cnt[15] ;
wire \inst4|acc[11] ;
wire \inst4|acc[10] ;
wire \inst4|acc[9] ;
wire \inst4|acc[8] ;
wire \inst4|acc[7] ;
wire \inst4|acc[6] ;
wire \inst4|acc[5] ;
wire \inst4|acc[4] ;
wire \inst4|acc[3] ;
wire \inst4|acc[2] ;
wire \inst4|acc[1] ;
wire \inst4|acc[0] ;
wire \inst4|acc[0]~105 ;
wire \inst4|acc[0]~104 ;
wire \inst4|acc[1]~107 ;
wire \inst4|acc[1]~106 ;
wire \inst4|acc[2]~109 ;
wire \inst4|acc[2]~108 ;
wire \inst4|acc[3]~111 ;
wire \inst4|acc[3]~110 ;
wire \inst4|acc[4]~113 ;
wire \inst4|acc[4]~112 ;
wire \inst4|acc[5]~115 ;
wire \inst4|acc[5]~114 ;
wire \inst4|acc[6]~117 ;
wire \inst4|acc[6]~116 ;
wire \inst4|acc[7]~119 ;
wire \inst4|acc[7]~118 ;
wire \inst4|acc[8]~121 ;
wire \inst4|acc[8]~120 ;
wire \inst4|acc[9]~123 ;
wire \inst4|acc[9]~122 ;
wire \inst4|acc[10]~125 ;
wire \inst4|acc[10]~124 ;
wire \inst4|acc[11]~127 ;
wire \inst4|acc[11]~126 ;
wire \inst4|acc[12]~128 ;
wire \inst3|cnt[14] ;
wire \inst3|cnt[13] ;
wire \inst3|cnt[12] ;
wire \inst3|cnt[11] ;
wire \inst3|cnt[10] ;
wire \inst3|cnt[9] ;
wire \inst3|cnt[8] ;
wire \inst3|cnt[7] ;
wire \inst3|cnt[6] ;
wire \inst3|cnt[5] ;
wire \inst3|cnt[4] ;
wire \inst3|cnt[3] ;
wire \inst3|cnt[2] ;
wire \inst3|cnt[1] ;
wire \inst3|cnt[0] ;
wire \inst3|cnt[0]~129 ;
wire \inst3|cnt[0]~128 ;
wire \inst3|cnt[1]~131 ;
wire \inst3|cnt[1]~130 ;
wire \inst3|cnt[2]~133 ;
wire \inst3|cnt[2]~132 ;
wire \inst3|cnt[3]~135 ;
wire \inst3|cnt[3]~134 ;
wire \inst3|cnt[4]~137 ;
wire \inst3|cnt[4]~136 ;
wire \inst3|cnt[5]~139 ;
wire \inst3|cnt[5]~138 ;
wire \inst3|cnt[6]~141 ;
wire \inst3|cnt[6]~140 ;
wire \inst3|cnt[7]~143 ;
wire \inst3|cnt[7]~142 ;
wire \inst3|cnt[8]~145 ;
wire \inst3|cnt[8]~144 ;
wire \inst3|cnt[9]~147 ;
wire \inst3|cnt[9]~146 ;
wire \inst3|cnt[10]~149 ;
wire \inst3|cnt[10]~148 ;
wire \inst3|cnt[11]~151 ;
wire \inst3|cnt[11]~150 ;
wire \inst3|cnt[12]~153 ;
wire \inst3|cnt[12]~152 ;
wire \inst3|cnt[13]~155 ;
wire \inst3|cnt[13]~154 ;
wire \inst3|cnt[14]~157 ;
wire \inst3|cnt[14]~156 ;
wire \inst3|cnt[15]~158 ;
wire \inst5|cnt[3] ;
wire \inst1|altsyncram_component|auto_generated|q_a[7] ;
wire \inst1|altsyncram_component|auto_generated|q_a[6] ;
wire \inst1|altsyncram_component|auto_generated|q_a[5] ;
wire \inst1|altsyncram_component|auto_generated|q_a[4] ;
wire \inst1|altsyncram_component|auto_generated|q_a[3] ;
wire \inst5|U1|u2|tsr[3] ;
wire \inst5|cnt[0] ;
wire \inst5|cnt[1] ;
wire \inst5|cnt[2] ;
wire \inst5|cnt_3_~COMBOUT ;
wire \inst5|U1|u2|un1_clk1x_enable13_2_a ;
wire \inst5|read_once_9_iv_i_0_a2_0_5 ;
wire \inst5|U1|u1|rbr[1] ;
wire \inst5|U1|u1|rbr[7] ;
wire \inst5|U1|u1|rbr_0_ ;
wire \inst5|U1|u1|rbr[5] ;
wire \inst5|U1|u1|rbr[6] ;
wire \inst5|U1|u1|rbr_4_ ;
wire \inst5|U1|u1|read_en_6_0_a4_1_x ;
wire \inst5|U1|u1|read_en_6_0_a4_a ;
wire \inst5|U1|u2|tbr[3] ;
wire \inst5|U1|u2|tsr[4] ;
wire \inst5|U1|u2|tsr_3_~COMBOUT ;
wire \inst5|cnt_0_~COMBOUT ;
wire \inst5|cnt_1_~COMBOUT ;
wire \inst5|cnt_2_~COMBOUT ;
wire \inst5|un1_rom_addr9_3_i_a ;
wire \inst5|un1_rom_addr9_3_i ;
wire \inst5|U1|u1|U1_u1_clkdiv[3] ;
wire \inst5|U1|u1|rsr[1] ;
wire \inst5|U1|u1|rsr[0] ;
wire \inst5|din[3] ;
wire \inst5|U1|u2|tbr[4] ;
wire \inst5|U1|u2|tsr[5] ;
wire \inst5|U1|u2|tsr_4_~COMBOUT ;
wire \inst5|U1|u1|clkdiv[2] ;
wire \inst5|U1|u1|clkdiv[1] ;
wire \inst5|U1|u1|clk1x_enable ;
wire \inst5|U1|u1|clkdiv[0] ;
wire \inst5|U1|u1|clkdiv_5_sum3_a ;
wire \inst5|U1|u1|clkdiv_3_~COMBOUT ;
wire \inst5|din[4] ;
wire \inst5|U1|u2|tbr[5] ;
wire \inst5|U1|u2|tsr[6] ;
wire \inst5|U1|u2|tsr_5_~COMBOUT ;
wire \inst5|U1|u1|clkdiv_2_~COMBOUT ;
wire \inst5|U1|u1|clkdiv_1_~COMBOUT ;
wire \inst5|U1|u1|clk1x_enable_Z~COMBOUT ;
wire \inst5|U1|u1|clkdiv_0_~COMBOUT ;
wire \inst5|din[5] ;
wire \inst5|U1|u2|tbr[6] ;
wire \inst5|U1|u2|tsr[7] ;
wire \inst5|U1|u2|tsr_6_~COMBOUT ;
wire \inst5|din[6] ;
wire \inst5|U1|u2|tbr[7] ;
wire \inst5|U1|u2|tsr_7_~COMBOUT ;
wire \inst5|din[7] ;
wire \inst5|cnt[3]~clkctrl ;
wire \inst4|acc[12]~clkctrl ;
wire \inst5|U1|u1|U1_u1_clkdiv[3]~clkctrl ;
wire \inst5|wrn_i_1~clkctrl ;
wire \inst5|U1|u1|rsr[1]~feeder ;
wire \inst5|U1|u1|rbr[1]~feeder ;
wire \inst5|U1|u1|rsr[0]~feeder ;
wire \inst5|U1|u1|rbr[7]~feeder ;
wire \inst5|U1|u1|rbr_4_~feeder ;
wire \inst5|U1|u2|tbr[3]~feeder ;
wire \inst5|din[3]~feeder ;
wire \inst5|U1|u2|tbr[4]~feeder ;
wire \inst5|din[4]~feeder ;
wire \inst5|U1|u2|tbr[5]~feeder ;
wire \inst5|U1|u2|tbr[6]~feeder ;
wire \inst5|din[6]~feeder ;
wire \inst5|U1|u2|tbr[7]~feeder ;
wire \inst5|din[7]~feeder ;
wire \inst5|U1|u2|clkdiv_0_~COMBOUT ;
wire \rst_n~combout ;
wire \inst3|rst_out ;
wire \inst3|rst_out~clkctrl ;
wire \inst5|U1|u2|clkdiv[0] ;
wire \inst5|U1|u2|clkdiv_1_~COMBOUT ;
wire \inst5|U1|u2|clkdiv[1] ;
wire \inst5|U1|u2|clkdiv_2_~COMBOUT ;
wire \inst5|U1|u2|clkdiv[2] ;
wire \inst5|U1|u2|clkdiv_3_~COMBOUT ;
wire \inst5|U1|u2|U1_u2_clkdiv[3] ;
wire \inst5|U1|u2|U1_u2_clkdiv[3]~clkctrl ;
wire \inst5|U1|u2|no_bits_sent_0_~COMBOUT ;
wire \inst5|U1|u2|no_bits_sent_1_~COMBOUT ;
wire \inst5|U1|u2|no_bits_sent_1 ;
wire \inst5|U1|u2|no_bits_sent_3_~COMBOUT ;
wire \inst5|U1|u2|no_bits_sent_3 ;
wire \inst5|U1|u2|tbre_0~COMBOUT ;
wire \inst5|U1|u2|no_bits_sent_2_~COMBOUT ;
wire \inst5|U1|u2|no_bits_sent_2 ;
wire \inst5|U1|u2|un1_clk1x_enable13_2_i ;
wire \inst5|U1|u2|tbre ;
wire \inst5|U1|u1|data_ready~feeder ;
wire \inst5|U1|u1|N_96_i ;
wire \inst5|U1|u1|no_bits_rcvd_1_~COMBOUT ;
wire \rxd~combout ;
wire \inst5|U1|u1|rxd1_i_0_Z~COMBOUT ;
wire \inst5|U1|u1|rxd1_i_0 ;
wire \inst5|U1|u1|rxd2_i ;
wire \inst5|U1|u1|clk1x_enable_0_Z~COMBOUT ;
wire \inst5|U1|u1|no_bits_rcvd_0_~COMBOUT ;
wire \inst5|U1|u1|no_bits_rcvd[0] ;
wire \inst5|U1|u1|no_bits_rcvd_3_~COMBOUT ;
wire \inst5|U1|u1|no_bits_rcvd[3] ;
wire \inst5|U1|u1|un1_clk1x_enable13_0_a ;
wire \inst5|U1|u1|N_396_i ;
wire \inst5|U1|u1|clk1x_enable_0 ;
wire \inst5|U1|u1|clk1x_enable_0~clkctrl ;
wire \inst5|U1|u1|no_bits_rcvd[1] ;
wire \inst5|U1|u1|no_bits_rcvd_2_~COMBOUT ;
wire \inst5|U1|u1|no_bits_rcvd[2] ;
wire \inst5|U1|u1|data_ready12_0_a2 ;
wire \inst5|U1|u1|data_ready ;
wire \inst5|rdn_d_i_0~feeder ;
wire \inst5|rdn_d_i_0 ;
wire \inst5|rdn_d2_i~feeder ;
wire \inst5|rdn_d2_i ;
wire \inst5|rdn_i_0_Z~COMBOUT ;
wire \inst5|rdn_i_0 ;
wire \inst5|U1|u1|rsr_7_~COMBOUT ;
wire \inst5|U1|u1|parity8_0_x2 ;
wire \inst5|U1|u1|rsr[7] ;
wire \inst5|U1|u1|rsr[6]~feeder ;
wire \inst5|U1|u1|rsr[6] ;
wire \inst5|U1|u1|rsr[5] ;
wire \inst5|U1|u1|rsr[4] ;
wire \inst5|U1|u1|rsr[3]~feeder ;
wire \inst5|U1|u1|rsr[3] ;
wire \inst5|U1|u1|rsr[2]~feeder ;
wire \inst5|U1|u1|rsr[2] ;
wire \inst5|U1|u1|rbr_1~feeder ;
wire \inst5|U1|u1|parity9_0_a3 ;
wire \inst5|U1|u1|rbr_1 ;
wire \inst5|U1|u1|rbr_2~feeder ;
wire \inst5|U1|u1|rbr_2 ;
wire \inst5|read_en_i_0_Z~COMBOUT ;
wire \inst5|rom_addr_d_0_~COMBOUT ;
wire \~GND ;
wire \inst5|read_en_i~COMBOUT ;
wire \inst5|read_en_i_0_0 ;
wire \inst5|rom_addr_d[0] ;
wire \inst5|rom_addr_d_cout[0] ;
wire \inst5|rom_addr_d_cout[1] ;
wire \inst5|rom_addr_d_2_~COMBOUT ;
wire \inst5|rom_addr_d[2] ;
wire \inst5|rom_addr_d_cout[2] ;
wire \inst5|rom_addr_d_cout[3] ;
wire \inst5|rom_addr_d_4_~COMBOUT ;
wire \inst5|rom_addr_d[4] ;
wire \inst5|rom_addr_d_cout[4] ;
wire \inst5|rom_addr_d_5_~COMBOUT ;
wire \inst5|rom_addr_d[5] ;
wire \inst5|rom_addr_d_cout[5] ;
wire \inst5|rom_addr_d_6_~COMBOUT ;
wire \inst5|rom_addr_d[6] ;
wire \inst5|rom_addr_6_~COMBOUT ;
wire \inst5|U1|u2|tsre_i_0~COMBOUT ;
wire \inst5|I_39_0 ;
wire \inst5|U1|u2|N_385_i ;
wire \inst5|U1|u2|tsre_i ;
wire \inst5|read_once_9_iv_i_0_a2_0_2_a_x ;
wire \inst5|read_once_9_iv_i_0_a2_0_2 ;
wire \inst5|read_once_Z~COMBOUT ;
wire \inst5|read_once ;
wire \inst5|N_103_i_i ;
wire \inst5|rom_addrz[6] ;
wire \inst5|rom_addr_d_3_~COMBOUT ;
wire \inst5|rom_addr_d[3] ;
wire \inst5|rom_addr_3_~COMBOUT ;
wire \inst5|rom_addrz[3] ;
wire \inst5|rom_addr_4_~COMBOUT ;
wire \inst5|rom_addrz[4] ;
wire \inst5|rom_addr_0_~COMBOUT ;
wire \inst5|rom_addrz[0] ;
wire \inst5|rom_addr_2_~COMBOUT ;
wire \inst5|rom_addrz[2] ;
wire \inst5|un1_rdn_1_0_a4_a ;
wire \inst5|un1_rdn_1_0_a4 ;
wire \inst5|N_376_1_i ;
wire \inst5|read_en_i_0 ;
wire \inst5|sclrun1_rom_addr9_1_0_a2 ;
wire \inst5|wrn_i_1 ;
wire \inst5|U1|u2|wrn1_i_0 ;
wire \inst5|U1|u2|wrn2_i~feeder ;
wire \inst5|U1|u2|wrn2_i ;
wire \inst5|U1|u2|clk1x_enable13 ;
wire \inst5|U1|u2|un17_clk1x_enable_a ;
wire \inst5|U1|u2|un17_clk1x_enable ;
wire \inst5|U1|u2|clk1x_enable ;
wire \inst5|U1|u2|N_383_i ;
wire \inst5|U1|u2|N_383_i~clkctrl ;
wire \inst5|U1|u2|no_bits_sent_0 ;
wire \inst5|I_43 ;
wire \inst5|U1|u2|tsr14 ;
wire \MCLK~combout ;
wire \MCLK~clkctrl ;
wire \inst5|rom_addr_d_1_~COMBOUT ;
wire \inst5|rom_addr_d[1] ;
wire \inst5|rom_addr_1_~COMBOUT ;
wire \inst5|rom_addrz[1] ;
wire \inst5|rom_addr_5_~COMBOUT ;
wire \inst5|rom_addrz[5] ;
wire \inst1|altsyncram_component|auto_generated|q_a[2] ;
wire \inst5|din[2] ;
wire \inst5|U1|u2|tbr[2] ;
wire \inst5|U1|u2|tsr_2_~COMBOUT ;
wire \inst5|U1|u2|N_485_i ;
wire \inst5|U1|u2|tsr[2] ;
wire \inst1|altsyncram_component|auto_generated|q_a[1] ;
wire \inst5|din[1]~feeder ;
wire \inst5|din[1] ;
wire \inst5|U1|u2|tbr[1]~feeder ;
wire \inst5|U1|u2|tbr[1] ;
wire \inst5|U1|u2|tsr_1_~COMBOUT ;
wire \inst5|U1|u2|tsr[1] ;
wire \inst1|altsyncram_component|auto_generated|q_a[0] ;
wire \inst5|din[0]~feeder ;
wire \inst5|din[0] ;
wire \inst5|U1|u2|tbr[0]~feeder ;
wire \inst5|U1|u2|tbr[0] ;
wire \inst5|U1|u2|tsr_0_~COMBOUT ;
wire \inst5|U1|u2|tsr_0 ;
wire \inst5|U1|u2|parity_i_0~COMBOUT ;
wire \inst5|U1|u2|tsr16 ;
wire \inst5|U1|u2|parity_i ;
wire \inst5|I_45 ;
wire \inst5|I_40_a ;
wire \inst5|U1|u2|sdo_i_Z~COMBOUT ;
wire \inst5|U1|u2|un1_tsr15_1_a_x ;
wire \inst5|U1|u2|N_380_i ;
wire \inst5|U1|u2|sdo_i ;

wire [7:0] \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

assign \inst1|altsyncram_component|auto_generated|q_a[0]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \inst1|altsyncram_component|auto_generated|q_a[1]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \inst1|altsyncram_component|auto_generated|q_a[2]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \inst1|altsyncram_component|auto_generated|q_a[3]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \inst1|altsyncram_component|auto_generated|q_a[4]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \inst1|altsyncram_component|auto_generated|q_a[5]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \inst1|altsyncram_component|auto_generated|q_a[6]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \inst1|altsyncram_component|auto_generated|q_a[7]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];

// atom is at LCFF_X1_Y13_N25
cycloneii_lcell_ff \inst4|acc[12]~I (
	.clk(\MCLK~clkctrl ),
	.datain(\inst4|acc[12]~128 ),
	.sdata(),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\inst4|acc[12] ));

// atom is at LCCOMB_X21_Y23_N10
cycloneii_lcell_comb \inst5|U1|u2|clkdiv_5_sum3_a_Z (
// Equation(s):
// \inst5|U1|u2|clkdiv_5_sum3_a  = !\inst5|U1|u2|clkdiv[0]  # !\inst5|U1|u2|clk1x_enable 

	.dataa(\inst5|U1|u2|clk1x_enable ),
	.datab(vcc),
	.datac(\inst5|U1|u2|clkdiv[0] ),
	.datad(vcc),
	.cin(gnd),
	.combout(\inst5|U1|u2|clkdiv_5_sum3_a ),
	.cout());
// synopsys translate_off
defparam \inst5|U1|u2|clkdiv_5_sum3_a_Z .sum_lutc_input = "datac";
defparam \inst5|U1|u2|clkdiv_5_sum3_a_Z .lut_mask = 16'h5F5F;
// synopsys translate_on

// atom is at LCFF_X19_Y19_N31
cycloneii_lcell_ff \inst3|cnt[15]~I (
	.clk(\inst4|acc[12]~clkctrl ),
	.datain(\inst3|cnt[15]~158 ),
	.sdata(),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\inst3|cnt[15] ));

// atom is at LCFF_X1_Y13_N23
cycloneii_lcell_ff \inst4|acc[11]~I (
	.clk(\MCLK~clkctrl ),
	.datain(\inst4|acc[11]~126 ),
	.sdata(),