uart_if_modelsim.xrf

S7_UART串口输出

instance = comp, \rst_n~I , rst_n, uart_if_rom, 1
instance = comp, \inst3|rst_out~I , inst3|rst_out, uart_if_rom, 1
instance = comp, \inst3|rst_out~clkctrl_I , inst3|rst_out~clkctrl, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_0_ , inst5|U1|u2|clkdiv_0_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_1_~0 , inst5|U1|u2|clkdiv_1_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_1_ , inst5|U1|u2|clkdiv_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_2_~0 , inst5|U1|u2|clkdiv_2_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_2_ , inst5|U1|u2|clkdiv_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_3_~0 , inst5|U1|u2|clkdiv_3_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_3_ , inst5|U1|u2|clkdiv_3_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|U1_u2_clkdiv[3]~clkctrl_I , inst5|U1|u2|U1_u2_clkdiv[3]~clkctrl, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_0_~0 , inst5|U1|u2|no_bits_sent_0_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_1_~0 , inst5|U1|u2|no_bits_sent_1_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_1_ , inst5|U1|u2|no_bits_sent_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_3_~0 , inst5|U1|u2|no_bits_sent_3_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_3_ , inst5|U1|u2|no_bits_sent_3_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbre_0~0 , inst5|U1|u2|tbre_0~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_2_~0 , inst5|U1|u2|no_bits_sent_2_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_2_ , inst5|U1|u2|no_bits_sent_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un1_clk1x_enable13_2 , inst5|U1|u2|un1_clk1x_enable13_2, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbre_0 , inst5|U1|u2|tbre_0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|data_ready~feeder_I , inst5|U1|u1|data_ready~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|un1_rst_i_a2_x , inst5|U1|u1|un1_rst_i_a2_x, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_1_~0 , inst5|U1|u1|no_bits_rcvd_1_~0, uart_if_rom, 1
instance = comp, \inst5|rxd_in , inst5|rxd_in, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rxd1_i_0_Z~0 , inst5|U1|u1|rxd1_i_0_Z~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rxd1_i_0_Z , inst5|U1|u1|rxd1_i_0_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rxd2_i_Z , inst5|U1|u1|rxd2_i_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clk1x_enable_0_Z~0 , inst5|U1|u1|clk1x_enable_0_Z~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_0_~0 , inst5|U1|u1|no_bits_rcvd_0_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_0_ , inst5|U1|u1|no_bits_rcvd_0_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_3_~0 , inst5|U1|u1|no_bits_rcvd_3_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_3_ , inst5|U1|u1|no_bits_rcvd_3_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|un1_clk1x_enable13_0_a_Z , inst5|U1|u1|un1_clk1x_enable13_0_a_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|un1_clk1x_enable13_0 , inst5|U1|u1|un1_clk1x_enable13_0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clk1x_enable_0_Z , inst5|U1|u1|clk1x_enable_0_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clk1x_enable_0~clkctrl_I , inst5|U1|u1|clk1x_enable_0~clkctrl, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_1_ , inst5|U1|u1|no_bits_rcvd_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_2_~0 , inst5|U1|u1|no_bits_rcvd_2_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|no_bits_rcvd_2_ , inst5|U1|u1|no_bits_rcvd_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|data_ready12_0_a2_Z , inst5|U1|u1|data_ready12_0_a2_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|data_ready_0 , inst5|U1|u1|data_ready_0, uart_if_rom, 1
instance = comp, \inst5|rdn_d_i_0~feeder_I , inst5|rdn_d_i_0~feeder, uart_if_rom, 1
instance = comp, \inst5|rdn_d_i_0_Z , inst5|rdn_d_i_0_Z, uart_if_rom, 1
instance = comp, \inst5|rdn_d2_i~feeder_I , inst5|rdn_d2_i~feeder, uart_if_rom, 1
instance = comp, \inst5|rdn_d2_i_Z , inst5|rdn_d2_i_Z, uart_if_rom, 1
instance = comp, \inst5|rdn_i_0_Z~0 , inst5|rdn_i_0_Z~0, uart_if_rom, 1
instance = comp, \inst5|rdn_i_0_Z , inst5|rdn_i_0_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_7_~0 , inst5|U1|u1|rsr_7_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|parity8_0_x2_Z , inst5|U1|u1|parity8_0_x2_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_7_ , inst5|U1|u1|rsr_7_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr[6]~feeder_I , inst5|U1|u1|rsr[6]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_6_ , inst5|U1|u1|rsr_6_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_5_ , inst5|U1|u1|rsr_5_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_4_ , inst5|U1|u1|rsr_4_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr[3]~feeder_I , inst5|U1|u1|rsr[3]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_3_ , inst5|U1|u1|rsr_3_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr[2]~feeder_I , inst5|U1|u1|rsr[2]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_2_ , inst5|U1|u1|rsr_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_1~feeder_I , inst5|U1|u1|rbr_1~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|parity9_0_a3_Z , inst5|U1|u1|parity9_0_a3_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_2_ , inst5|U1|u1|rbr_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_2~feeder_I , inst5|U1|u1|rbr_2~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_3_ , inst5|U1|u1|rbr_3_, uart_if_rom, 1
instance = comp, \inst5|read_en_i_0_Z~0 , inst5|read_en_i_0_Z~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_0_~0 , inst5|rom_addr_d_0_~0, uart_if_rom, 1
instance = comp, \~GND~I , ~GND, uart_if_rom, 1
instance = comp, \inst5|read_en_i~0 , inst5|read_en_i~0, uart_if_rom, 1
instance = comp, \inst5|read_en_i , inst5|read_en_i, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_0_ , inst5|rom_addr_d_0_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_1_~0 , inst5|rom_addr_d_1_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_2_~0 , inst5|rom_addr_d_2_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_2_ , inst5|rom_addr_d_2_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_3_~0 , inst5|rom_addr_d_3_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_4_~0 , inst5|rom_addr_d_4_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_4_ , inst5|rom_addr_d_4_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_5_~0 , inst5|rom_addr_d_5_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_5_ , inst5|rom_addr_d_5_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_6_~0 , inst5|rom_addr_d_6_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_6_ , inst5|rom_addr_d_6_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_6_~0 , inst5|rom_addr_6_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsre_i_0~0 , inst5|U1|u2|tsre_i_0~0, uart_if_rom, 1
instance = comp, \inst5|I_39_0_Z , inst5|I_39_0_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un13_tsre , inst5|U1|u2|un13_tsre, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsre_i_0 , inst5|U1|u2|tsre_i_0, uart_if_rom, 1
instance = comp, \inst5|read_once_9_iv_i_0_a2_0_2_a_x_Z , inst5|read_once_9_iv_i_0_a2_0_2_a_x_Z, uart_if_rom, 1
instance = comp, \inst5|read_once_9_iv_i_0_a2_0_2_Z , inst5|read_once_9_iv_i_0_a2_0_2_Z, uart_if_rom, 1
instance = comp, \inst5|read_once_Z~0 , inst5|read_once_Z~0, uart_if_rom, 1
instance = comp, \inst5|read_once_Z , inst5|read_once_Z, uart_if_rom, 1
instance = comp, \inst5|un1_read_en_2_i , inst5|un1_read_en_2_i, uart_if_rom, 1
instance = comp, \inst5|rom_addr_6_ , inst5|rom_addr_6_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_3_ , inst5|rom_addr_d_3_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_3_~0 , inst5|rom_addr_3_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_3_ , inst5|rom_addr_3_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_4_~0 , inst5|rom_addr_4_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_4_ , inst5|rom_addr_4_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_0_~0 , inst5|rom_addr_0_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_0_ , inst5|rom_addr_0_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_2_~0 , inst5|rom_addr_2_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_2_ , inst5|rom_addr_2_, uart_if_rom, 1
instance = comp, \inst5|un1_rdn_1_0_a4_a_Z , inst5|un1_rdn_1_0_a4_a_Z, uart_if_rom, 1
instance = comp, \inst5|un1_rdn_1_0_a4_Z , inst5|un1_rdn_1_0_a4_Z, uart_if_rom, 1
instance = comp, \inst5|un1_rdn_1_0_1 , inst5|un1_rdn_1_0_1, uart_if_rom, 1
instance = comp, \inst5|read_en_i_0_Z , inst5|read_en_i_0_Z, uart_if_rom, 1
instance = comp, \inst5|wrn_i_0_Z~0 , inst5|wrn_i_0_Z~0, uart_if_rom, 1
instance = comp, \inst5|wrn_i_0_Z , inst5|wrn_i_0_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|wrn1_i_0_Z , inst5|U1|u2|wrn1_i_0_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|wrn2_i~feeder_I , inst5|U1|u2|wrn2_i~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|wrn2_i_Z , inst5|U1|u2|wrn2_i_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clk1x_enable_Z~0 , inst5|U1|u2|clk1x_enable_Z~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un17_clk1x_enable_a_Z , inst5|U1|u2|un17_clk1x_enable_a_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un17_clk1x_enable_Z , inst5|U1|u2|un17_clk1x_enable_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clk1x_enable_Z , inst5|U1|u2|clk1x_enable_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un1_rst_x , inst5|U1|u2|un1_rst_x, uart_if_rom, 1
instance = comp, \inst5|U1|u2|N_383_i~clkctrl_I , inst5|U1|u2|N_383_i~clkctrl, uart_if_rom, 1
instance = comp, \inst5|U1|u2|no_bits_sent_0_ , inst5|U1|u2|no_bits_sent_0_, uart_if_rom, 1
instance = comp, \inst5|I_43_Z , inst5|I_43_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr14_Z , inst5|U1|u2|tsr14_Z, uart_if_rom, 1
instance = comp, \MCLK~I , MCLK, uart_if_rom, 1
instance = comp, \MCLK~clkctrl_I , MCLK~clkctrl, uart_if_rom, 1
instance = comp, \inst5|rom_addr_d_1_ , inst5|rom_addr_d_1_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_1_~0 , inst5|rom_addr_1_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_1_ , inst5|rom_addr_1_, uart_if_rom, 1
instance = comp, \inst5|rom_addr_5_~0 , inst5|rom_addr_5_~0, uart_if_rom, 1
instance = comp, \inst5|rom_addr_5_ , inst5|rom_addr_5_, uart_if_rom, 1
instance = comp, \inst5|din_2_ , inst5|din_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_2_ , inst5|U1|u2|tbr_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_2_~0 , inst5|U1|u2|tsr_2_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un20_tsr , inst5|U1|u2|un20_tsr, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_2_ , inst5|U1|u2|tsr_2_, uart_if_rom, 1
instance = comp, \inst5|din[1]~feeder_I , inst5|din[1]~feeder, uart_if_rom, 1
instance = comp, \inst5|din_1_ , inst5|din_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr[1]~feeder_I , inst5|U1|u2|tbr[1]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_1_ , inst5|U1|u2|tbr_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_1_~0 , inst5|U1|u2|tsr_1_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_1_ , inst5|U1|u2|tsr_1_, uart_if_rom, 1
instance = comp, \inst5|din[0]~feeder_I , inst5|din[0]~feeder, uart_if_rom, 1
instance = comp, \inst5|din_0_ , inst5|din_0_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr[0]~feeder_I , inst5|U1|u2|tbr[0]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_0_ , inst5|U1|u2|tbr_0_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_0_~0 , inst5|U1|u2|tsr_0_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_0_ , inst5|U1|u2|tsr_0_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|parity_i_0~0 , inst5|U1|u2|parity_i_0~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr16_Z , inst5|U1|u2|tsr16_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|parity_i_0 , inst5|U1|u2|parity_i_0, uart_if_rom, 1
instance = comp, \inst5|I_45_Z , inst5|I_45_Z, uart_if_rom, 1
instance = comp, \inst5|I_40_a_Z , inst5|I_40_a_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|sdo_i_Z~0 , inst5|U1|u2|sdo_i_Z~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un1_tsr15_1_a_x_Z , inst5|U1|u2|un1_tsr15_1_a_x_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un1_tsr15_1_x , inst5|U1|u2|un1_tsr15_1_x, uart_if_rom, 1
instance = comp, \inst5|U1|u2|sdo_i_Z , inst5|U1|u2|sdo_i_Z, uart_if_rom, 1
instance = comp, \inst5|txd_out , inst5|txd_out, uart_if_rom, 1