uart_if_modelsim.xrf

S7_UART串口输出

vendor_name = ModelSim
source_file = 1, E:/code/EP2C20/S5_UART/sythesis/uart_if.vqm
source_file = 1, E:/code/EP2C20/S5_UART/src/div1_8m.v
source_file = 1, E:/code/EP2C20/S5_UART/physical/uart_if_rom.bdf
source_file = 1, E:/code/EP2C20/S5_UART/physical/uart_rom.mif
source_file = 1, E:/code/EP2C20/S5_UART/Src/filter.v
source_file = 1, E:/code/EP2C20/S5_UART/physical/uart_rom.v
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
source_file = 1, c:/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/lpm_mux.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/lpm_decode.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/aglobal50.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altsyncram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/a_rdenreg.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altrom.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altdpram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altqpram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/cbx.lst
source_file = 1, E:/code/EP2C20/S5_UART/physical/db/altsyncram_2dq.tdf
design_name = uart_if_rom
instance = comp, \inst4|acc[12]~I , inst4|acc[12], uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_5_sum3_a_Z , inst5|U1|u2|clkdiv_5_sum3_a_Z, uart_if_rom, 1
instance = comp, \inst3|cnt[15]~I , inst3|cnt[15], uart_if_rom, 1
instance = comp, \inst4|acc[11]~I , inst4|acc[11], uart_if_rom, 1
instance = comp, \inst4|acc[10]~I , inst4|acc[10], uart_if_rom, 1
instance = comp, \inst4|acc[9]~I , inst4|acc[9], uart_if_rom, 1
instance = comp, \inst4|acc[8]~I , inst4|acc[8], uart_if_rom, 1
instance = comp, \inst4|acc[7]~I , inst4|acc[7], uart_if_rom, 1
instance = comp, \inst4|acc[6]~I , inst4|acc[6], uart_if_rom, 1
instance = comp, \inst4|acc[5]~I , inst4|acc[5], uart_if_rom, 1
instance = comp, \inst4|acc[4]~I , inst4|acc[4], uart_if_rom, 1
instance = comp, \inst4|acc[3]~I , inst4|acc[3], uart_if_rom, 1
instance = comp, \inst4|acc[2]~I , inst4|acc[2], uart_if_rom, 1
instance = comp, \inst4|acc[1]~I , inst4|acc[1], uart_if_rom, 1
instance = comp, \inst4|acc[0]~I , inst4|acc[0], uart_if_rom, 1
instance = comp, \inst4|acc[0]~104_I , inst4|acc[0]~104, uart_if_rom, 1
instance = comp, \inst4|acc[1]~106_I , inst4|acc[1]~106, uart_if_rom, 1
instance = comp, \inst4|acc[2]~108_I , inst4|acc[2]~108, uart_if_rom, 1
instance = comp, \inst4|acc[3]~110_I , inst4|acc[3]~110, uart_if_rom, 1
instance = comp, \inst4|acc[4]~112_I , inst4|acc[4]~112, uart_if_rom, 1
instance = comp, \inst4|acc[5]~114_I , inst4|acc[5]~114, uart_if_rom, 1
instance = comp, \inst4|acc[6]~116_I , inst4|acc[6]~116, uart_if_rom, 1
instance = comp, \inst4|acc[7]~118_I , inst4|acc[7]~118, uart_if_rom, 1
instance = comp, \inst4|acc[8]~120_I , inst4|acc[8]~120, uart_if_rom, 1
instance = comp, \inst4|acc[9]~122_I , inst4|acc[9]~122, uart_if_rom, 1
instance = comp, \inst4|acc[10]~124_I , inst4|acc[10]~124, uart_if_rom, 1
instance = comp, \inst4|acc[11]~126_I , inst4|acc[11]~126, uart_if_rom, 1
instance = comp, \inst4|acc[12]~128_I , inst4|acc[12]~128, uart_if_rom, 1
instance = comp, \inst3|cnt[14]~I , inst3|cnt[14], uart_if_rom, 1
instance = comp, \inst3|cnt[13]~I , inst3|cnt[13], uart_if_rom, 1
instance = comp, \inst3|cnt[12]~I , inst3|cnt[12], uart_if_rom, 1
instance = comp, \inst3|cnt[11]~I , inst3|cnt[11], uart_if_rom, 1
instance = comp, \inst3|cnt[10]~I , inst3|cnt[10], uart_if_rom, 1
instance = comp, \inst3|cnt[9]~I , inst3|cnt[9], uart_if_rom, 1
instance = comp, \inst3|cnt[8]~I , inst3|cnt[8], uart_if_rom, 1
instance = comp, \inst3|cnt[7]~I , inst3|cnt[7], uart_if_rom, 1
instance = comp, \inst3|cnt[6]~I , inst3|cnt[6], uart_if_rom, 1
instance = comp, \inst3|cnt[5]~I , inst3|cnt[5], uart_if_rom, 1
instance = comp, \inst3|cnt[4]~I , inst3|cnt[4], uart_if_rom, 1
instance = comp, \inst3|cnt[3]~I , inst3|cnt[3], uart_if_rom, 1
instance = comp, \inst3|cnt[2]~I , inst3|cnt[2], uart_if_rom, 1
instance = comp, \inst3|cnt[1]~I , inst3|cnt[1], uart_if_rom, 1
instance = comp, \inst3|cnt[0]~I , inst3|cnt[0], uart_if_rom, 1
instance = comp, \inst3|cnt[0]~128_I , inst3|cnt[0]~128, uart_if_rom, 1
instance = comp, \inst3|cnt[1]~130_I , inst3|cnt[1]~130, uart_if_rom, 1
instance = comp, \inst3|cnt[2]~132_I , inst3|cnt[2]~132, uart_if_rom, 1
instance = comp, \inst3|cnt[3]~134_I , inst3|cnt[3]~134, uart_if_rom, 1
instance = comp, \inst3|cnt[4]~136_I , inst3|cnt[4]~136, uart_if_rom, 1
instance = comp, \inst3|cnt[5]~138_I , inst3|cnt[5]~138, uart_if_rom, 1
instance = comp, \inst3|cnt[6]~140_I , inst3|cnt[6]~140, uart_if_rom, 1
instance = comp, \inst3|cnt[7]~142_I , inst3|cnt[7]~142, uart_if_rom, 1
instance = comp, \inst3|cnt[8]~144_I , inst3|cnt[8]~144, uart_if_rom, 1
instance = comp, \inst3|cnt[9]~146_I , inst3|cnt[9]~146, uart_if_rom, 1
instance = comp, \inst3|cnt[10]~148_I , inst3|cnt[10]~148, uart_if_rom, 1
instance = comp, \inst3|cnt[11]~150_I , inst3|cnt[11]~150, uart_if_rom, 1
instance = comp, \inst3|cnt[12]~152_I , inst3|cnt[12]~152, uart_if_rom, 1
instance = comp, \inst3|cnt[13]~154_I , inst3|cnt[13]~154, uart_if_rom, 1
instance = comp, \inst3|cnt[14]~156_I , inst3|cnt[14]~156, uart_if_rom, 1
instance = comp, \inst3|cnt[15]~158_I , inst3|cnt[15]~158, uart_if_rom, 1
instance = comp, \inst5|cnt_3_ , inst5|cnt_3_, uart_if_rom, 1
instance = comp, \inst1|altsyncram_component|auto_generated|ram_block1a0 , inst1|altsyncram_component|auto_generated|ram_block1a0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_3_ , inst5|U1|u2|tsr_3_, uart_if_rom, 1
instance = comp, \inst5|cnt_0_ , inst5|cnt_0_, uart_if_rom, 1
instance = comp, \inst5|cnt_1_ , inst5|cnt_1_, uart_if_rom, 1
instance = comp, \inst5|cnt_2_ , inst5|cnt_2_, uart_if_rom, 1
instance = comp, \inst5|cnt_3_~0 , inst5|cnt_3_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|un1_clk1x_enable13_2_a_Z , inst5|U1|u2|un1_clk1x_enable13_2_a_Z, uart_if_rom, 1
instance = comp, \inst5|read_once_9_iv_i_0_a2_0_5_Z , inst5|read_once_9_iv_i_0_a2_0_5_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_1_ , inst5|U1|u1|rbr_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_7_ , inst5|U1|u1|rbr_7_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_0_~I , inst5|U1|u1|rbr_0_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_5_ , inst5|U1|u1|rbr_5_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_6_ , inst5|U1|u1|rbr_6_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_4_~I , inst5|U1|u1|rbr_4_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_4_~0 , inst5|U1|u1|rbr_4_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_0_~0 , inst5|U1|u1|rbr_0_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_3_ , inst5|U1|u2|tbr_3_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_4_ , inst5|U1|u2|tsr_4_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_3_~0 , inst5|U1|u2|tsr_3_~0, uart_if_rom, 1
instance = comp, \inst5|cnt_0_~0 , inst5|cnt_0_~0, uart_if_rom, 1
instance = comp, \inst5|cnt_1_~0 , inst5|cnt_1_~0, uart_if_rom, 1
instance = comp, \inst5|cnt_2_~0 , inst5|cnt_2_~0, uart_if_rom, 1
instance = comp, \inst5|un1_rom_addr9_3_i_a_Z , inst5|un1_rom_addr9_3_i_a_Z, uart_if_rom, 1
instance = comp, \inst5|un1_rom_addr9_3_i_Z , inst5|un1_rom_addr9_3_i_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_3_ , inst5|U1|u1|clkdiv_3_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_1_ , inst5|U1|u1|rsr_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr_0_ , inst5|U1|u1|rsr_0_, uart_if_rom, 1
instance = comp, \inst5|din_3_ , inst5|din_3_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_4_ , inst5|U1|u2|tbr_4_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_5_ , inst5|U1|u2|tsr_5_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_4_~0 , inst5|U1|u2|tsr_4_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_2_ , inst5|U1|u1|clkdiv_2_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_1_ , inst5|U1|u1|clkdiv_1_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clk1x_enable_Z , inst5|U1|u1|clk1x_enable_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_0_ , inst5|U1|u1|clkdiv_0_, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_5_sum3_a_Z , inst5|U1|u1|clkdiv_5_sum3_a_Z, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_3_~0 , inst5|U1|u1|clkdiv_3_~0, uart_if_rom, 1
instance = comp, \inst5|din_4_ , inst5|din_4_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_5_ , inst5|U1|u2|tbr_5_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_6_ , inst5|U1|u2|tsr_6_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_5_~0 , inst5|U1|u2|tsr_5_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_2_~0 , inst5|U1|u1|clkdiv_2_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_1_~0 , inst5|U1|u1|clkdiv_1_~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clk1x_enable_Z~0 , inst5|U1|u1|clk1x_enable_Z~0, uart_if_rom, 1
instance = comp, \inst5|U1|u1|clkdiv_0_~0 , inst5|U1|u1|clkdiv_0_~0, uart_if_rom, 1
instance = comp, \inst5|din_5_ , inst5|din_5_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_6_ , inst5|U1|u2|tbr_6_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_7_ , inst5|U1|u2|tsr_7_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_6_~0 , inst5|U1|u2|tsr_6_~0, uart_if_rom, 1
instance = comp, \inst5|din_6_ , inst5|din_6_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr_7_ , inst5|U1|u2|tbr_7_, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tsr_7_~0 , inst5|U1|u2|tsr_7_~0, uart_if_rom, 1
instance = comp, \inst5|din_7_ , inst5|din_7_, uart_if_rom, 1
instance = comp, \inst5|cnt[3]~clkctrl_I , inst5|cnt[3]~clkctrl, uart_if_rom, 1
instance = comp, \inst4|acc[12]~clkctrl_I , inst4|acc[12]~clkctrl, uart_if_rom, 1
instance = comp, \inst5|U1|u1|U1_u1_clkdiv[3]~clkctrl_I , inst5|U1|u1|U1_u1_clkdiv[3]~clkctrl, uart_if_rom, 1
instance = comp, \inst5|wrn_i_1~clkctrl_I , inst5|wrn_i_1~clkctrl, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr[1]~feeder_I , inst5|U1|u1|rsr[1]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr[1]~feeder_I , inst5|U1|u1|rbr[1]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rsr[0]~feeder_I , inst5|U1|u1|rsr[0]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr[7]~feeder_I , inst5|U1|u1|rbr[7]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u1|rbr_4_~feeder_I , inst5|U1|u1|rbr_4_~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr[3]~feeder_I , inst5|U1|u2|tbr[3]~feeder, uart_if_rom, 1
instance = comp, \inst5|din[3]~feeder_I , inst5|din[3]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr[4]~feeder_I , inst5|U1|u2|tbr[4]~feeder, uart_if_rom, 1
instance = comp, \inst5|din[4]~feeder_I , inst5|din[4]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr[5]~feeder_I , inst5|U1|u2|tbr[5]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr[6]~feeder_I , inst5|U1|u2|tbr[6]~feeder, uart_if_rom, 1
instance = comp, \inst5|din[6]~feeder_I , inst5|din[6]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|tbr[7]~feeder_I , inst5|U1|u2|tbr[7]~feeder, uart_if_rom, 1
instance = comp, \inst5|din[7]~feeder_I , inst5|din[7]~feeder, uart_if_rom, 1
instance = comp, \inst5|U1|u2|clkdiv_0_~0 , inst5|U1|u2|clkdiv_0_~0, uart_if_rom, 1