mem_interface_top_top_0.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

		ctrl_ddr_cas_L		: out std_logic;
		ctrl_ddr_we_L		: out std_logic;
		ctrl_ddr_cs_L		: out std_logic;
		ctrl_ddr_cke		: out std_logic;
		dummy_write_pattern	: out std_logic;
		burst_length		: out std_logic_vector(2 downto 0)
	    );
end component;



signal wr_df_data		: std_logic_vector((data_width*2 -1) downto 0);
signal mask_df_data		: std_logic_vector((data_mask_width*2 -1) downto 0);
signal rd_data_rise		: std_logic_vector((data_width -1) downto 0);
signal rd_data_fall		: std_logic_vector((data_width -1) downto 0);
signal af_empty_w		: std_logic;
signal dq_tap_sel_done		: std_logic;
signal af_addr			: std_logic_vector(35 downto 0);
signal ctrl_af_rden		: std_logic;
signal ctrl_wr_df_rden		: std_logic;
signal ctrl_dummy_rden		: std_logic;
signal ctrl_dqs_enable		: std_logic;
signal ctrl_dqs_reset		: std_logic;
signal ctrl_wr_en		: std_logic;
signal ctrl_rden		: std_logic;
signal dqs_idelay_inc		: std_logic_vector((ReadEnable-1) downto 0);                       
signal dqs_idelay_ce		: std_logic_vector((ReadEnable-1) downto 0);                       
signal dqs_idelay_rst		: std_logic_vector((ReadEnable-1) downto 0);                       
signal data_idelay_inc		: std_logic_vector((ReadEnable-1) downto 0);
signal data_idelay_ce		: std_logic_vector((ReadEnable-1) downto 0);
signal data_idelay_rst		: std_logic_vector((ReadEnable-1) downto 0);
signal wr_en			: std_logic;
signal dqs_rst			: std_logic;
signal dqs_en			: std_logic;
signal wr_data_rise		: std_logic_vector((data_width -1) downto 0);
signal wr_data_fall		: std_logic_vector((data_width -1) downto 0);
signal dqs_delayed		: std_logic_vector((data_strobe_width-1) downto 0);
signal mask_data_fall		: std_logic_vector((data_mask_width-1) downto 0);
signal mask_data_rise		: std_logic_vector((data_mask_width-1) downto 0);
signal ctrl_ddr_address		: std_logic_vector((row_address - 1) downto 0); 
signal ctrl_ddr_ba		: std_logic_vector((bank_address - 1) downto 0);
signal ctrl_ddr_ras_L		: std_logic;
signal ctrl_ddr_cas_L		: std_logic;
signal ctrl_ddr_we_L		: std_logic;
signal ctrl_ddr_cs_L		: std_logic; 
signal ctrl_ddr_cke		: std_logic;
signal comp_done		: std_logic;
signal dummy_write_pattern	: std_logic;



begin

CLK_TB   <= clk_0;      
RESET_TB <= sys_rst; 



data_path_00: mem_interface_top_data_path_0 port map
	      ( 
		CLK			=> clk_0,
		CLK90			=> clk_90,
		CAL_CLK			=> clk_50,
		RESET0			=> sys_rst,
		RESET90			=> sys_rst90,
		RESET_CAL_CLK		=> sys_rst_ref_clk_1,
		idelay_ctrl_rdy		=> idelay_ctrl_rdy,
		dummy_write_pattern	=> dummy_write_pattern,
		CTRL_DUMMYREAD_START	=> ctrl_dummy_rden,
		WDF_DATA		=> wr_df_data,
		MASK_DATA		=> mask_df_data,
		CTRL_WREN		=> ctrl_wr_en,
		CTRL_DQS_RST		=> ctrl_dqs_reset,
		CTRL_DQS_EN		=> ctrl_dqs_enable,
		dqs_delayed		=> dqs_delayed,           
		data_idelay_inc		=> data_idelay_inc,
		data_idelay_ce		=> data_idelay_ce,
		data_idelay_rst		=> data_idelay_rst,
		dqs_idelay_inc		=> dqs_idelay_inc,
		dqs_idelay_ce		=> dqs_idelay_ce,
		dqs_idelay_rst		=> dqs_idelay_rst,
		SEL_DONE		=> dq_tap_sel_done,
		dqs_rst			=> dqs_rst,
		dqs_en			=> dqs_en,
		wr_en			=> wr_en,			
		wr_data_rise		=> wr_data_rise,		
		wr_data_fall		=> wr_data_fall,		
		mask_data_rise		=> mask_data_rise,		
		mask_data_fall          => mask_data_fall        
	);				 
					 
iobs_00: mem_interface_top_iobs_0	port map		 
	    ( CAL_CLK			=> clk_50,
	      DDR_CK             	=> DDR_CK,
	      DDR_CK_N           	=> DDR_CK_N,
	      CLK                	=> clk_0,
	      CLK90              	=> clk_90,
	      RESET0			=> sys_rst,
	      RESET90            	=> sys_rst90,
	      dqs_idelay_inc     	=> dqs_idelay_inc,    
	      dqs_idelay_ce      	=> dqs_idelay_ce,    
	      dqs_idelay_rst     	=> dqs_idelay_rst,    
	      data_idelay_inc		=> data_idelay_inc,	
	      data_idelay_ce     	=> data_idelay_ce,    
	      data_idelay_rst    	=> data_idelay_rst,   
	      dqs_rst			=> dqs_rst,		
	      dqs_en             	=> dqs_en,         
	      wr_en              	=> wr_en,   
	      wr_data_rise       	=> wr_data_rise,   
	      wr_data_fall       	=> wr_data_fall,   
	      mask_data_rise		=> mask_data_rise,	
	      mask_data_fall     	=> mask_data_fall, 
	      rd_data_rise       	=> rd_data_rise,      
	      rd_data_fall       	=> rd_data_fall,      
	      dqs_delayed        	=> dqs_delayed,       
	      DDR_DQ			=> DDR_DQ,		
	      DDR_DQS            	=> DDR_DQS,           
	      DDR_DM             	=> DDR_DM,            
	      ctrl_ddr_address   	=> ctrl_ddr_address,  
	      ctrl_ddr_ba		=> ctrl_ddr_ba,	
	      ctrl_ddr_ras_L     	=> ctrl_ddr_ras_L,    
	      ctrl_ddr_cas_L     	=> ctrl_ddr_cas_L,    
	      ctrl_ddr_we_L      	=> ctrl_ddr_we_L,     
	      ctrl_ddr_cs_L      	=> ctrl_ddr_cs_L,     
	      ctrl_ddr_cke		=> ctrl_ddr_cke,	
	      DDR_ADDRESS        	=> DDR_A,
	      DDR_BA             	=> DDR_BA,
	      DDR_RAS_L          	=> DDR_RAS_N,
	      DDR_CAS_L          	=> DDR_CAS_N,
	      DDR_WE_L			=> DDR_WE_N,
	      DDR_CKE            	=> DDR_CKE,
	      ddr_cs_L            	=> DDR_CS_N
	    );				
					
user_interface_00: mem_interface_top_user_interface_0 port map
	    ( CLK			=> clk_0,
	      clk90               	=> clk_90,
	      RESET               	=> sys_rst,
	      ctrl_rden			=> ctrl_rden,
	      READ_DATA_RISE		=> rd_data_rise,
	      READ_DATA_FALL      	=> rd_data_fall,
	      READ_DATA_FIFO_OUT	=> READ_DATA_FIFO_OUT,
	      comp_done			=> comp_done,
	      READ_DATA_VALID		=> READ_DATA_VALID,
	      AF_EMPTY			=> af_empty_w,
	      AF_ALMOST_FULL		=> AF_ALMOST_FULL,	
	      APP_AF_ADDR		=> APP_AF_ADDR,	
	      APP_AF_WREN		=> APP_AF_WREN,	
	      CTRL_AF_RDEN        	=> ctrl_af_rden,
	      AF_ADDR			=> af_addr,
	      APP_WDF_DATA		=> APP_WDF_DATA,
	      APP_MASK_DATA		=> APP_MASK_DATA,	
	      APP_WDF_WREN		=> APP_WDF_WREN,
	      CTRL_WDF_RDEN       	=> ctrl_wr_df_rden,
	      WDF_DATA			=> wr_df_data,
	      MASK_DATA           	=> mask_df_data,
	      WDF_ALMOST_FULL		=> WDF_ALMOST_FULL
	     );				
					
ddr_controller_00:  mem_interface_top_ddr_controller_0 port map
	     ( 				
		clk_0			=> clk_0,
		refresh_clk		=> ref_clk,
		rst			=> sys_rst,
		af_addr			=> af_addr,
		af_empty		=> af_empty_w,
		phy_Dly_Slct_Done	=> dq_tap_sel_done,
		comp_done		=> comp_done,
		ctrl_Dummyread_Start	=> ctrl_dummy_rden,
		ctrl_af_RdEn		=> ctrl_af_rden,
		ctrl_Wdf_RdEn		=> ctrl_wr_df_rden,
		ctrl_Dqs_Rst		=> ctrl_dqs_reset,
		ctrl_Dqs_En		=> ctrl_dqs_enable,
		ctrl_WrEn		=> ctrl_wr_en,
		ctrl_RdEn		=> ctrl_rden,
		ctrl_ddr_address	=> ctrl_ddr_address,
		ctrl_ddr_ba		=> ctrl_ddr_ba,	
		ctrl_ddr_ras_L		=> ctrl_ddr_ras_L,	
		ctrl_ddr_cas_L		=> ctrl_ddr_cas_L,	
		ctrl_ddr_we_L		=> ctrl_ddr_we_L,	
		ctrl_ddr_cs_L		=> ctrl_ddr_cs_L,	
		ctrl_ddr_cke		=> ctrl_ddr_cke,
		dummy_write_pattern	=> dummy_write_pattern,
		burst_length		=> BURST_LENGTH
	    );	

	    
end arch;