📄 mem_interface_top_top_0.vhd
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-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.6
-- \ \ Application : MIG
-- / / Filename: mem_interface_top_top_0.vhd
-- /___/ /\ Date Last Modified: Wed Jun 1 2005
-- \ \ / \Date Created: Mon May 2 2005
-- \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Instantiates the main design logic of memory interface and interfaces
-- with the user.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.mem_interface_top_parameters_0.all;
entity mem_interface_top_top_0 is
port( clk_0 : in std_logic;
clk_90 : in std_logic;
clk_50 : in std_logic;
ref_clk : in std_logic;
idelay_ctrl_rdy : in std_logic;
sys_rst_ref_clk_1 : in std_logic;
sys_rst : in std_logic;
sys_rst90 : in std_logic;
DDR_RAS_N : out std_logic;
DDR_CAS_N : out std_logic;
DDR_WE_N : out std_logic;
DDR_CKE : out std_logic;
DDR_CS_N : out std_logic;
DDR_DQ : inout std_logic_vector((data_width-1) downto 0);
DDR_DQS : inout std_logic_vector((data_strobe_width-1) downto 0);
DDR_DM : out std_logic_vector((data_mask_width-1) downto 0);
APP_MASK_DATA : in std_logic_vector((data_mask_width*2 -1) downto 0);
DDR_CK : out std_logic_vector((clk_width-1) downto 0);
DDR_CK_N : out std_logic_vector((clk_width-1) downto 0);
DDR_BA : out std_logic_vector((bank_address-1) downto 0);
DDR_A : out std_logic_vector((row_address-1) downto 0);
WDF_ALMOST_FULL : out std_logic;
AF_ALMOST_FULL : out std_logic;
BURST_LENGTH : out std_logic_vector(2 downto 0);
READ_DATA_VALID : out std_logic;
READ_DATA_FIFO_OUT : out std_logic_vector((data_width*2 -1) downto 0);
APP_AF_ADDR : in std_logic_vector(35 downto 0);
APP_AF_WREN : in std_logic;
APP_WDF_DATA : in std_logic_vector((data_width*2 -1) downto 0);
APP_WDF_WREN : in std_logic;
CLK_TB : out std_logic;
RESET_TB : out std_logic
);
end mem_interface_top_top_0;
architecture arch of mem_interface_top_top_0 is
component mem_interface_top_data_path_0
port(
CLK : in std_logic;
CLK90 : in std_logic;
CAL_CLK : in std_logic;
RESET0 : in std_logic;
RESET90 : in std_logic;
RESET_CAL_CLK : in std_logic;
idelay_ctrl_rdy : in std_logic;
dummy_write_pattern : in std_logic;
CTRL_DUMMYREAD_START : in std_logic;
WDF_DATA : in std_logic_vector((data_width*2 -1) downto 0);
MASK_DATA : in std_logic_vector((data_mask_width*2 -1) downto 0);
CTRL_WREN : in std_logic;
CTRL_DQS_RST : in std_logic;
CTRL_DQS_EN : in std_logic;
dqs_delayed : in std_logic_vector((data_strobe_width -1) downto 0);
data_idelay_inc : out std_logic_vector((ReadEnable - 1) downto 0);
data_idelay_ce : out std_logic_vector((ReadEnable - 1) downto 0);
data_idelay_rst : out std_logic_vector((ReadEnable - 1) downto 0);
dqs_idelay_inc : out std_logic_vector((ReadEnable - 1) downto 0);
dqs_idelay_ce : out std_logic_vector((ReadEnable - 1) downto 0);
dqs_idelay_rst : out std_logic_vector((ReadEnable - 1) downto 0);
SEL_DONE : out std_logic;
dqs_rst : out std_logic;
dqs_en : out std_logic;
wr_en : out std_logic;
wr_data_rise : out std_logic_vector((data_width -1) downto 0);
wr_data_fall : out std_logic_vector((data_width -1) downto 0);
mask_data_rise : out std_logic_vector((data_mask_width -1) downto 0);
mask_data_fall : out std_logic_vector((data_mask_width -1) downto 0)
);
end component;
component mem_interface_top_iobs_0
port( CAL_CLK : in std_logic;
DDR_CK : out std_logic_vector((clk_width-1) downto 0);
DDR_CK_N : out std_logic_vector((clk_width-1) downto 0);
CLK : in std_logic;
CLK90 : in std_logic;
RESET0 : in std_logic;
RESET90 : in std_logic;
dqs_idelay_inc : in std_logic_vector((ReadEnable-1) downto 0);
dqs_idelay_ce : in std_logic_vector((ReadEnable-1) downto 0);
dqs_idelay_rst : in std_logic_vector((ReadEnable-1) downto 0);
data_idelay_inc : in std_logic_vector((ReadEnable-1) downto 0);
data_idelay_ce : in std_logic_vector((ReadEnable-1) downto 0);
data_idelay_rst : in std_logic_vector((ReadEnable-1) downto 0);
dqs_rst : in std_logic;
dqs_en : in std_logic;
wr_en : in std_logic;
wr_data_rise : in std_logic_vector((data_width-1) downto 0);
wr_data_fall : in std_logic_vector((data_width-1) downto 0);
mask_data_rise : in std_logic_vector((data_mask_width-1) downto 0);
mask_data_fall : in std_logic_vector((data_mask_width-1) downto 0);
rd_data_rise : out std_logic_vector((data_width-1) downto 0);
rd_data_fall : out std_logic_vector((data_width-1) downto 0);
dqs_delayed : out std_logic_vector((data_strobe_width-1) downto 0);
DDR_DQ : inout std_logic_vector((data_width-1) downto 0);
DDR_DQS : inout std_logic_vector((data_strobe_width-1) downto 0);
DDR_DM : out std_logic_vector((data_mask_width-1) downto 0);
ctrl_ddr_address : in std_logic_vector((row_address-1) downto 0);
ctrl_ddr_ba : in std_logic_vector((bank_address-1) downto 0);
ctrl_ddr_ras_L : in std_logic;
ctrl_ddr_cas_L : in std_logic;
ctrl_ddr_we_L : in std_logic;
ctrl_ddr_cs_L : in std_logic;
ctrl_ddr_cke : in std_logic;
DDR_ADDRESS : out std_logic_vector((row_address-1) downto 0);
DDR_BA : out std_logic_vector((bank_address-1) downto 0);
DDR_RAS_L : out std_logic;
DDR_CAS_L : out std_logic;
DDR_WE_L : out std_logic;
DDR_CKE : out std_logic;
ddr_cs_L : out std_logic
);
end component;
component mem_interface_top_user_interface_0
port( CLK : in std_logic;
clk90 : in std_logic;
RESET : in std_logic;
ctrl_rden : in std_logic;
READ_DATA_RISE : in std_logic_vector((data_width -1) downto 0);
READ_DATA_FALL : in std_logic_vector((data_width -1) downto 0);
READ_DATA_FIFO_OUT : out std_logic_vector((data_width*2 -1) downto 0);
comp_done : out std_logic;
READ_DATA_VALID : out std_logic;
AF_EMPTY : out std_logic;
AF_ALMOST_FULL : out std_logic;
APP_AF_ADDR : in std_logic_vector(35 downto 0);
APP_AF_WREN : in std_logic;
CTRL_AF_RDEN : in std_logic;
AF_ADDR : out std_logic_vector(35 downto 0);
APP_WDF_DATA : in std_logic_vector((data_width*2 -1) downto 0);
APP_MASK_DATA : in std_logic_vector((data_mask_width*2 -1) downto 0);
APP_WDF_WREN : in std_logic;
CTRL_WDF_RDEN : in std_logic;
WDF_DATA : out std_logic_vector((data_width*2 -1) downto 0);
MASK_DATA : out std_logic_vector((data_mask_width*2 -1) downto 0);
WDF_ALMOST_FULL : out std_logic
);
end component;
component mem_interface_top_ddr_controller_0
port(
clk_0 : in std_logic;
refresh_clk : in std_logic;
rst : in std_logic;
af_addr : in std_logic_vector(35 downto 0);
af_empty : in std_logic;
comp_done : in std_logic;
phy_Dly_Slct_Done : in std_logic;
ctrl_Dummyread_Start : out std_logic;
ctrl_af_RdEn : out std_logic;
ctrl_Wdf_RdEn : out std_logic;
ctrl_Dqs_Rst : out std_logic;
ctrl_Dqs_En : out std_logic;
ctrl_WrEn : out std_logic;
ctrl_RdEn : out std_logic;
ctrl_ddr_address : out std_logic_vector((row_address - 1) downto 0);
ctrl_ddr_ba : out std_logic_vector((bank_address - 1) downto 0);
ctrl_ddr_ras_L : out std_logic;
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