mem_interface_top_infrastructure.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_infrastructure.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Instantiates the DCM of the FPGA device. The system clock is given 
--		as the input and two clocks that are phase shifted by 90 degrees are taken out.
--		It also give the reset signals in phase with the clocks.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity mem_interface_top_infrastructure is
	port
	(
	 
	  
 	  
				  clk_0           : in std_logic;
				  clk_90          : in std_logic;
				  clk_50          : in std_logic;
				  dcm_lock        : in std_logic;


	      SYS_RESET_IN     	: in std_logic;

	      

	      sys_rst          	: out std_logic;
	      sys_rst90         : out std_logic;
	      sys_rst_ref_clk_1 : out std_logic
	    );
end mem_interface_top_infrastructure;

architecture arch of mem_interface_top_infrastructure is









signal sys_rst_0        : std_logic;  
signal sys_rst_1        : std_logic;  
signal sys_rst_2        : std_logic;  
signal sys_rst_3        : std_logic;  
signal sys_rst90_0      : std_logic;  
signal sys_rst90_1      : std_logic;  
signal sys_rst90_2      : std_logic;  
signal sys_rst90_3      : std_logic;  
signal sys_rst_ref_clk_0: std_logic;  
signal sys_rst_ref_clk_2: std_logic;  
signal sys_rst_ref_clk  : std_logic;  
signal REF_CLK200_IN	: std_logic; 
signal SYS_RESET    	: std_logic; 
signal clk_int          : std_logic;
signal clk90_int        : std_logic;
signal clk50_int        : std_logic;



begin



clk_int     <= clk_0;  
clk90_int   <= clk_90; 
clk50_int   <= clk_50; 
SYS_RESET   <= not SYS_RESET_IN;







process(clk_int)
begin
 if(clk_int'event and clk_int = '1') then
  if((SYS_RESET = '1') or  
(dcm_lock = '0')
 or (sys_rst_ref_clk = '1')) then
	sys_rst_0 <= '1';
	sys_rst_1 <= '1';
	sys_rst_2 <= '1';
	sys_rst_3 <= '1';
	sys_rst   <= '1';
  else
	sys_rst_0 <= '0';
	sys_rst_1 <= sys_rst_0;
	sys_rst_2 <= sys_rst_1;
	sys_rst_3 <= sys_rst_2;
	sys_rst   <= sys_rst_3;
  end if;
 end if;
end process;

process(clk90_int)
begin
 if(clk90_int'event and clk90_int = '1') then
  if((SYS_RESET = '1') or  
(dcm_lock = '0')
 or (sys_rst_ref_clk = '1')) then
      sys_rst90_0 <= '1';
      sys_rst90_1 <= '1';
      sys_rst90_2 <= '1';
      sys_rst90_3 <= '1';
      sys_rst90   <= '1';
  else
      sys_rst90_0 <= '0';
      sys_rst90_1 <= sys_rst90_0;
      sys_rst90_2 <= sys_rst90_1;
      sys_rst90_3 <= sys_rst90_2;
      sys_rst90   <= sys_rst90_3;
  end if;
 end if;
end process;

process(clk50_int)
begin
 if(clk50_int'event and clk50_int = '1') then
  if ((SYS_RESET = '1') or  
(dcm_lock = '0')
) then
      sys_rst_ref_clk_0 <= '1';
      sys_rst_ref_clk_1 <= '1';
      sys_rst_ref_clk_2 <= '1';
      sys_rst_ref_clk   <= '1';
  else
      sys_rst_ref_clk_0 <= '0';
      sys_rst_ref_clk_1 <= sys_rst_ref_clk_0;
      sys_rst_ref_clk_2 <= sys_rst_ref_clk_0;
      sys_rst_ref_clk   <= sys_rst_ref_clk_2;
  end if;
 end if;
end process;


end arch;