mem_interface_top.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

--------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- 
-- Device: Virtex-4
-- Design Name: DDR1_V4
-- Description     : It is the top most module which interfaces with the system 
-- 			   and the memory.
-------------------------------------------------------------------------------*/

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity mem_interface_top is 
port (
clk_200 : in std_logic;
cntrl0_DDR_DQ : inout  std_logic_vector(15  downto 0);
cntrl0_DDR_A : out  std_logic_vector(12  downto 0);
cntrl0_DDR_BA : out  std_logic_vector(1  downto 0);
cntrl0_DDR_CKE : out std_logic;
cntrl0_DDR_CS_N : out std_logic;
cntrl0_DDR_RAS_N : out std_logic;
cntrl0_DDR_CAS_N : out std_logic;
cntrl0_DDR_WE_N : out std_logic;
cntrl0_DDR_DM : out  std_logic_vector(1  downto 0);
cntrl0_ERROR : out std_logic;
SYS_RESET_IN : in std_logic;
clk_0 : in std_logic;
clk_90 : in std_logic;
clk_50 : in std_logic;
ref_clk : in std_logic;
dcm_lock : in std_logic;
cntrl0_DDR_DQS : inout  std_logic_vector(1  downto 0);
cntrl0_DDR_CK : out  std_logic_vector(0  downto 0);
cntrl0_DDR_CK_N : out  std_logic_vector(0  downto 0)
      );

end mem_interface_top;

architecture mem_interface_top_arc_mem_interface_top of mem_interface_top is




 COMPONENT mem_interface_top_main_0  port (DDR_DQ : inout  std_logic_vector(15  downto 0);
DDR_A : out  std_logic_vector(12  downto 0);
DDR_BA : out  std_logic_vector(1  downto 0);
DDR_CKE : out std_logic;
DDR_CS_N : out std_logic;
DDR_RAS_N : out std_logic;
DDR_CAS_N : out std_logic;
DDR_WE_N : out std_logic;
DDR_DM : out  std_logic_vector(1  downto 0);
ERROR : out std_logic;
DDR_DQS : inout  std_logic_vector(1  downto 0);
DDR_CK : out  std_logic_vector(0  downto 0);
DDR_CK_N : out  std_logic_vector(0  downto 0);
clk_0 : in std_logic;
clk_90 : in std_logic;
clk_50 : in std_logic;
ref_clk : in std_logic;

  sys_rst           : in std_logic;
  sys_rst90         : in std_logic;
  sys_rst_ref_clk_1 : in std_logic;
  idelay_ctrl_rdy   : in std_logic
);
END COMPONENT;




component mem_interface_top_infrastructure
	port( 	    
	
	     
	      sys_rst          	: out std_logic;
	      sys_rst90         : out std_logic;
	      sys_rst_ref_clk_1 : out std_logic;
	       SYS_RESET_IN : in std_logic;
clk_0 : in std_logic;
clk_90 : in std_logic;
clk_50 : in std_logic;
dcm_lock : in std_logic
      );
end component;

component mem_interface_top_idelay_ctrl
port (
      CLK200     : in std_logic;
      RESET      : in std_logic;
      RDY_STATUS : out std_logic
      );
end component;

signal sys_rst    : std_logic;
signal sys_rst90  : std_logic;
signal sys_rst_ref_clk_1 : std_logic;
signal idelay_ctrl_rdy : std_logic;


begin
    
main_00 :    mem_interface_top_main_0 port map (DDR_DQ	=> cntrl0_DDR_DQ,
DDR_A	=> cntrl0_DDR_A,
DDR_BA	=> cntrl0_DDR_BA,
DDR_CKE => cntrl0_DDR_CKE,
DDR_CS_N => cntrl0_DDR_CS_N,
DDR_RAS_N => cntrl0_DDR_RAS_N,
DDR_CAS_N => cntrl0_DDR_CAS_N,
DDR_WE_N => cntrl0_DDR_WE_N,
DDR_DM	=> cntrl0_DDR_DM,
ERROR => cntrl0_ERROR,
DDR_DQS	=> cntrl0_DDR_DQS,
DDR_CK	=> cntrl0_DDR_CK,
DDR_CK_N	=> cntrl0_DDR_CK_N,
clk_0 => clk_0,
clk_90 => clk_90,
clk_50 => clk_50,
ref_clk => ref_clk,

  sys_rst           => sys_rst,
  sys_rst90         => sys_rst90,
  sys_rst_ref_clk_1 => sys_rst_ref_clk_1,
  idelay_ctrl_rdy   => idelay_ctrl_rdy
);



				

infrastructure0: mem_interface_top_infrastructure	port map
	    ( 
	      sys_rst          	=> sys_rst,
	      sys_rst90         => sys_rst90,        
	      sys_rst_ref_clk_1 => sys_rst_ref_clk_1,
	      SYS_RESET_IN => SYS_RESET_IN,
clk_0	=> clk_0,
clk_90	=> clk_90,
clk_50	=> clk_50,
dcm_lock => dcm_lock
	    );	


  --//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-- IDELAYCTRL instantiation
--//////////////////////////////////////////////////////////////////////////////////////////////////////////////////

mem_interface_top_idelay_ctrl0 : mem_interface_top_idelay_ctrl 
               port map (
                         CLK200     => clk_200,
	                 RESET      => sys_rst,
	                 RDY_STATUS => idelay_ctrl_rdy 
                        );
                        
end mem_interface_top_arc_mem_interface_top;