mem_interface_top_cmp_rd_data_0.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_cmp_rd_data_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Contains the comaprison logic for the read data and generation of 
--		an error flag.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.mem_interface_top_parameters_0.all;

entity mem_interface_top_cmp_rd_data_0 is
	port(	CLK			: in std_logic;
		RESET			: in std_logic;
		READ_DATA_VALID		: in std_logic;
		APP_COMPARE_DATA	: in std_logic_vector((data_width*2 -1) downto 0);
		READ_DATA_FIFO_OUT	: in std_logic_vector((data_width*2 -1) downto 0);
		ERROR			: out std_logic
	 );
end mem_interface_top_cmp_rd_data_0;

architecture arch of mem_interface_top_cmp_rd_data_0 is

signal valid			: std_logic;
signal byte_err_rising		: std_logic_vector((data_width/8 -1) downto 0);
signal byte_err_falling		: std_logic_vector((data_width/8 -1) downto 0);
signal byte_err_rising_w	: std_logic_vector((data_width/8 -1) downto 0);
signal byte_err_falling_w	: std_logic_vector((data_width/8 -1) downto 0);
signal valid_1			: std_logic;
signal read_data_r		: std_logic_vector((data_width*2 -1) downto 0);
signal read_data_r2		: std_logic_vector((data_width*2 -1) downto 0);
signal write_data_r2		: std_logic_vector((data_width*2 -1) downto 0);
signal data_pattern_falling	: std_logic_vector((data_width -1) downto 0);
signal data_pattern_rising	: std_logic_vector((data_width -1) downto 0);
signal data_falling		: std_logic_vector((data_width -1) downto 0);
signal data_rising		: std_logic_vector((data_width -1) downto 0);
signal falling_error		: std_logic;
signal rising_error		: std_logic;
signal byte_err_rising_a	: std_logic;
signal byte_err_falling_a	: std_logic;
signal check			: std_logic_vector((data_width/8 -1) downto 0);

begin

check <= (others => '0');

data_falling         <= read_data_r2((data_width - 1) downto 0);
data_rising          <= read_data_r2((data_width*2 - 1) downto data_width);
data_pattern_falling <= write_data_r2((data_width - 1) downto 0);
data_pattern_rising  <= write_data_r2((data_width*2 - 1) downto data_width);

 
byte_err_falling_w(0) <= '1' when (valid_1 = '1') and (data_falling(7 downto 0) /= data_pattern_falling(7 downto 0)) else '0';

 
byte_err_falling_w(1) <= '1' when (valid_1 = '1') and (data_falling(15 downto 8) /= data_pattern_falling(15 downto 8)) else '0';



byte_err_rising_w(0)  <= '1' when (valid_1 = '1') and (data_rising(7 downto 0) /= data_pattern_rising(7 downto 0)) else '0';


byte_err_rising_w(1)  <= '1' when (valid_1 = '1') and (data_rising(15 downto 8) /= data_pattern_rising(15 downto 8)) else '0';


byte_err_rising_a     <=   '1' when (byte_err_rising(((data_width/8) -1) downto 0) /= check(((data_width/8) -1) downto 0)) else '0';

byte_err_falling_a    <=   '1' when (byte_err_falling(((data_width/8) -1) downto 0) /= check(((data_width/8) -1) downto 0)) else '0';

process(CLK)
begin
 if(CLK'event and CLK = '1') then
	byte_err_rising  <= byte_err_falling_w;
	byte_err_falling <= byte_err_rising_w;
 end if;
end process;

process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(RESET = '1') then
	rising_error	<= '0';
	falling_error	<= '0';
	ERROR		<= '0';
 else
	rising_error  <= byte_err_rising_a;
	falling_error <= byte_err_falling_a;
	ERROR         <= rising_error or falling_error; 
 end if;
assert (rising_error = '0' and falling_error = '0') report " DATA ERROR" severity warning;
end if;
end process;

process(CLK)
begin
 if(CLK'event and CLK = '1') then
  if(RESET = '1') then
	read_data_r <= (others => '0');
  else
	read_data_r <= READ_DATA_FIFO_OUT;
  end if;
 end if;
end process;

process(CLK)
begin
 if(CLK'event and CLK = '1') then
  if(RESET = '1') then
	read_data_r2	<= (others => '0');
	write_data_r2	<= (others => '0');
  else
	read_data_r2		<= read_data_r;
	write_data_r2		<= APP_COMPARE_DATA;
  end if;
 end if;
end process;

process(CLK)
begin
 if(CLK'event and CLK = '1') then
  if(RESET = '1') then
	valid   <= '0';
	valid_1 <= '0';
  else
	valid   <= READ_DATA_VALID;    
	valid_1 <= valid;
  end if;
 end if;
end process;

end arch;