mem_interface_top_backend_rom_0.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_backend_rom_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: It instantiates the addr_gen and the data_gen modules. It takes the 
--		user data stored in internal FIFOs and gives the data that is to 
--		be compared with the read data.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.mem_interface_top_parameters_0.all;

entity mem_interface_top_backend_rom_0 is
	port ( clk0			: in std_logic;                                                       
	       rst			: in std_logic;                      
	       -- enables signals from state machine                         
	       bkend_data_en		: in std_logic;
	       bkend_wraddr_en		: in std_logic;
	       bkend_rd_data_valid	: in std_logic;                      
	       --Write address fifo signals                                  
	       app_af_addr		: out std_logic_vector(35 downto 0);
	       app_af_WrEn		: out std_logic; 
	       --Write data fifo signals                                     
	       app_Wdf_data		: out std_logic_vector((data_width*2 -1) downto 0);
	       app_mask_data		: out std_logic_vector((data_mask_width*2 -1) downto 0);
	       app_compare_data		: out std_logic_vector((data_width*2 -1) downto 0);-- data for the backend compare logic       
	       app_Wdf_WrEn		: out std_logic                                               
	       );                               
end mem_interface_top_backend_rom_0;

architecture arch of mem_interface_top_backend_rom_0 is

component mem_interface_top_addr_gen 
	port	(
                    clk0		: in std_logic;
                    rst			: in std_logic;
                    bkend_wraddr_en	: in std_logic;
                    app_af_addr		: out std_logic_vector(35 downto 0);
                    app_af_WrEn		: out std_logic
                );
end component;

component mem_interface_top_data_gen_16
	port (
		clk0	: in std_logic;
		rst	: in std_logic;
		bkend_data_en : in std_logic;
		bkend_rd_data_valid : in std_logic;
		app_Wdf_data : out std_logic_vector(31 downto 0);
		app_mask_data : out std_logic_vector(3 downto 0);
		app_compare_data : out std_logic_vector(31 downto 0);
		app_Wdf_WrEn : out std_logic
	 );
end component;



component mem_interface_top_data_gen_8
	port (
		clk0	: in std_logic;
		rst	: in std_logic;
		bkend_data_en : in std_logic;
		bkend_rd_data_valid : in std_logic;
		app_Wdf_data : out std_logic_vector(15 downto 0);
		app_mask_data : out std_logic_vector(1 downto 0);
		app_compare_data : out std_logic_vector(15 downto 0);
		app_Wdf_WrEn : out std_logic
	 );
end component;	


signal app_Wdf_WrEn_w : std_logic_vector((fifo_16 - 1) downto 0);


signal app_Wdf_data0  : std_logic_vector(31 downto 0);




signal app_mask_data0 : std_logic_vector(3 downto 0);




signal app_compare_data0 : std_logic_vector(31 downto 0);




begin

app_Wdf_data <=   app_Wdf_data0(31 downto 16)   & 
		  app_Wdf_data0(15 downto 0)  ;

app_mask_data <=   app_mask_data0(3 downto 2)   & 
		   app_mask_data0(1 downto 0)  ;

app_compare_data <=   app_compare_data0(31 downto 16)   &
		      app_compare_data0(15 downto 0)  ;

app_Wdf_WrEn <= app_Wdf_WrEn_w(0);

addr_gen0: mem_interface_top_addr_gen port map(
                    clk0		=> clk0,
                    rst			=> rst,
                    bkend_wraddr_en	=> bkend_wraddr_en,
                    app_af_addr		=> app_af_addr,
                    app_af_WrEn		=> app_af_WrEn
                );

                  
data_gen_160: mem_interface_top_data_gen_16 port map(
		clk0				=> clk0,
		rst					=> rst,
		bkend_data_en		=> bkend_data_en,
		bkend_rd_data_valid	=> bkend_rd_data_valid,
		app_Wdf_data		=> app_Wdf_data0(31 downto 0),
		app_mask_data		=> app_mask_data0(3 downto 0),
		app_compare_data	=> app_compare_data0(31 downto 0),
		app_Wdf_WrEn		=> app_Wdf_WrEn_w(0)
	 );





end arch;