mem_interface_top_data_gen_16.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_data_gen_16.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Contains the data generation logic for a 16 bit data.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity mem_interface_top_data_gen_16 is
	port ( clk0			: in std_logic;                                                  
	       rst			: in std_logic;                  
	       -- enables signals from state machine                     
	       bkend_data_en		: in std_logic;
	       bkend_rd_data_valid	: in std_logic;
	       --Write data fifo signals                                 
	       app_Wdf_data		: out std_logic_vector(31 downto 0);
	       app_mask_data		: out std_logic_vector(3 downto 0);
	       app_compare_data		: out std_logic_vector(31 downto 0);
	       -- data for the backend compare logic   
	       app_Wdf_WrEn		: out std_logic
	       );                           
end mem_interface_top_data_gen_16;

architecture arch of mem_interface_top_data_gen_16 is

signal wr_state : bit_vector(1 downto 0);
signal rd_state : bit_vector(1 downto 0);
signal wr_data_pattern  : std_logic_vector(15 downto 0);
signal rd_data_pattern  : std_logic_vector(15 downto 0);
signal app_Wdf_WrEn_r	: std_logic;
signal app_Wdf_WrEn_2r	: std_logic;
signal app_Wdf_WrEn_3r	: std_logic;
signal bkend_rd_data_valid_r : std_logic;
signal app_Wdf_data_r	: std_logic_vector(31  downto 0) ;
signal app_Wdf_data_1r	: std_logic_vector(31  downto 0);
signal app_Wdf_data_2r	: std_logic_vector(31  downto 0);
signal app_mask_data_r  : std_logic_vector(3 downto 0) ;
signal app_mask_data_1r  : std_logic_vector(3 downto 0);
signal app_mask_data_2r  : std_logic_vector(3 downto 0);
signal rd_rising_edge_data : std_logic_vector(15 downto 0);
signal rd_falling_edge_data : std_logic_vector(15 downto 0);
signal wr_data_mask_rise	: std_logic_vector(1 downto 0);
signal wr_data_mask_fall	: std_logic_vector(1 downto 0);

constant wr_idle_first_data : bit_vector(1 downto 0) := "00";
constant wr_second_data     : bit_vector(1 downto 0) := "01";
constant wr_third_data      : bit_vector(1 downto 0) := "10";
constant wr_fourth_data     : bit_vector(1 downto 0) := "11";

constant rd_idle_first_data : bit_vector(1 downto 0) := "00";
constant rd_second_data     : bit_vector(1 downto 0) := "01";
constant rd_third_data      : bit_vector(1 downto 0) := "10";
constant rd_fourth_data     : bit_vector(1 downto 0) := "11";


begin

wr_data_mask_rise <= "00"; 
wr_data_mask_fall <= "00"; 

--DATA generation for WRITE DATA FIFOs & for READ DATA COMPARE

--write data generation
process(clk0)
begin
 if(clk0'event and clk0 = '1') then
  if(rst = '1')then
	wr_data_pattern <= "0000000000000000";
	wr_state	<= wr_idle_first_data;
  else
	case wr_state is
		when wr_idle_first_data =>
			if(bkend_data_en = '1') then
				wr_data_pattern <= "1111111111111111";
				wr_state	<= wr_second_data;
			else 
				wr_state	<= wr_idle_first_data;
			end if;

		when wr_second_data =>
			if(bkend_data_en = '1') then
				wr_data_pattern <= "1010101010101010";
				wr_state	<= wr_third_data;
			else
				wr_state	<= wr_second_data;
			end if;

		when wr_third_data =>
			if(bkend_data_en = '1') then
				wr_data_pattern <= "0101010101010101";
				wr_state	<= wr_fourth_data;
			else
				wr_state	<= wr_third_data;
			end if;

		when wr_fourth_data =>
			if(bkend_data_en = '1') then
				wr_data_pattern <= "1001100110011001";
				wr_state	<= wr_idle_first_data;
			else
				wr_state	<= wr_fourth_data;
			end if;
	end case;
  end if;
 end if;
end process;
	
app_Wdf_data_r <= (wr_data_pattern(15 downto 0) & not(wr_data_pattern(15 downto 0))) when (app_Wdf_WrEn_r = '1') else
                  (others => '0');               

app_mask_data_r <= (wr_data_mask_rise & wr_data_mask_fall) when (app_Wdf_WrEn_r = '1') else
		   "0000";

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
  if(rst = '1')then
      app_Wdf_data_1r <= (others => '0');
      app_Wdf_data_2r <= (others => '0');
      app_Wdf_data    <= (others => '0');
  else
      app_Wdf_data_1r <= app_Wdf_data_r ;
      app_Wdf_data_2r <= app_Wdf_data_1r;
      app_Wdf_data    <= app_Wdf_data_2r;
  end if;
 end if;
end process;

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
  if(rst = '1')then
	app_mask_data_1r <= (others => '0'); 
	app_mask_data_2r <= (others => '0'); 
	app_mask_data    <= (others => '0'); 
  else
	app_mask_data_1r <= app_mask_data_r ;
	app_mask_data_2r <= app_mask_data_1r;
	app_mask_data    <= app_mask_data_2r;
  end if;
 end if;
end process;

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
  if(rst = '1')then
	app_Wdf_WrEn_r	<= '0';	
	app_Wdf_WrEn_2r <= '0';
	app_Wdf_WrEn_3r <= '0';
	app_Wdf_WrEn	<= '0';
  else
	app_Wdf_WrEn_r	<= bkend_data_en;
	app_Wdf_WrEn_2r <= app_Wdf_WrEn_r;
	app_Wdf_WrEn_3r <= app_Wdf_WrEn_2r;
	app_Wdf_WrEn	<= app_Wdf_WrEn_3r;
  end if;
 end if;
end process;

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
  if(rst = '1')then
	bkend_rd_data_valid_r <= '0';
  else
	bkend_rd_data_valid_r <= bkend_rd_data_valid;
  end if;
 end if;
end process;

--read comparison data generation
process(clk0)
begin
 if(clk0'event and clk0 = '1') then
  if(rst = '1')then
	rd_data_pattern <= "0000000000000000";
	rd_state	<= rd_idle_first_data;
  else
	case rd_state is
		when rd_idle_first_data =>
			if(bkend_rd_data_valid = '1') then
				rd_data_pattern <= "1111111111111111";
				rd_state	<= rd_second_data;
			else 
				rd_state	<= rd_idle_first_data;
			end if;

		when rd_second_data =>
			if(bkend_rd_data_valid = '1') then
				rd_data_pattern <= "1010101010101010";
				rd_state	<= rd_third_data;
			else
				rd_state	<= rd_second_data;
			end if;

		when rd_third_data =>
			if(bkend_rd_data_valid = '1') then
				rd_data_pattern <= "0101010101010101";
				rd_state	<= rd_fourth_data;
			else
				rd_state	<= rd_third_data;
			end if;

		when rd_fourth_data =>
			if(bkend_rd_data_valid = '1') then
				rd_data_pattern <= "1001100110011001";
				rd_state	<= rd_idle_first_data;
			else
				rd_state	<= rd_fourth_data;
			end if;
	end case;
  end if;
 end if;
end process;

rd_rising_edge_data  <= rd_data_pattern;    
rd_falling_edge_data <= not(rd_data_pattern);   

--data to the compare circuit during read
app_compare_data <= (rd_rising_edge_data & rd_falling_edge_data) when (bkend_rd_data_valid_r = '1') else
                    (others => '0');                                                                       

end arch;