📄 mem_interface_top_ddr_controller_0.vhd
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process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
ctrl_Dqs_En_r1 <= '0';
else
ctrl_Dqs_En_r1 <= ctrl_Dqs_En_r;
end if;
end if;
end process;
ctrl_Dqs_En <= ctrl_Dqs_En_r1 when (REGISTERED_VALUE = '1') else
ctrl_Dqs_En_r;
-- cas count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
cas_count(2 downto 0) <= "000";
elsif ((init_state = INIT_DUMMY_FIRST_READ)) then
cas_count(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) + registered;
elsif (cas_count(2 downto 0) /= "000") then
cas_count(2 downto 0) <= cas_count(2 downto 0) - 1;
else cas_count(2 downto 0) <= "000";
end if;
end if;
end process;
--dummy_read enable
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
dummy_read_en <= '0';
elsif (init_state = INIT_DUMMY_READ) then
dummy_read_en <= '1';
elsif (phy_Dly_Slct_Done = '1') then
dummy_read_en <= '0';
else dummy_read_en <= dummy_read_en;
end if;
end if;
end process;
-- ctrl_Dummyread_Start signal generation to the data path module
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
ctrl_Dummyread_Start_r1 <= '0';
elsif ((dummy_read_en = '1') and (cas_count = "000")) then
ctrl_Dummyread_Start_r1 <= '1';
elsif (phy_Dly_Slct_Done = '1') then
ctrl_Dummyread_Start_r1 <= '0';
else ctrl_Dummyread_Start_r1 <= ctrl_Dummyread_Start_r1;
end if;
end if;
end process;
-- register ctrl_Dummyread_Start signal
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
ctrl_Dummyread_Start_r2 <= '0';
ctrl_Dummyread_Start_r3 <= '0';
ctrl_Dummyread_Start_r4 <= '0';
ctrl_Dummyread_Start <= '0';
else
ctrl_Dummyread_Start_r2 <= ctrl_Dummyread_Start_r1;
ctrl_Dummyread_Start_r3 <= ctrl_Dummyread_Start_r2;
ctrl_Dummyread_Start_r4 <= ctrl_Dummyread_Start_r3;
ctrl_Dummyread_Start <= ctrl_Dummyread_Start_r4;
end if;
end if;
end process;
-- read_wait/write_wait to idle count
-- the state machine waits for 15 clock cycles in the write wait state for any wr/rd commands
-- to be issued. If no commands are issued in 15 clock cycles, the statemachine issues
-- enters the idle state and stays in the idle state until an auto refresh is required.
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
idle_cnt(3 downto 0) <= "0000";
elsif (read_write_state = '1') then
idle_cnt(3 downto 0) <= "1111" ;
elsif (idle_cnt(3 downto 0) /= "0000") then
idle_cnt(3 downto 0) <= idle_cnt(3 downto 0) - 1;
else idle_cnt(3 downto 0) <= "0000";
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
cas_check_count(3 downto 0) <= "0000";
elsif (first_read_state_r2 = '1' or pattern_read_state_r2 = '1') then
cas_check_count(3 downto 0) <= (CAS_LATENCY_VALUE - 1);
elsif (cas_check_count(3 downto 0) /= "0000") then
cas_check_count(3 downto 0) <= cas_check_count(3 downto 0) - 1;
else
cas_check_count(3 downto 0) <= "0000";
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst = '1') then
rdburst_cnt(2 downto 0) <= "000";
ctrl_RdEn_r <= '0';
elsif ((cas_check_count = "0001") and (burst_read_state_r3 = '0')) then
rdburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
ctrl_RdEn_r <= '1';
elsif(burst_read_state_r3 = '1' or pattern_read_state_r3 = '1') then
if(burst_cnt = "0100") then
rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) + burst_cnt_by2;--burst_cnt(2 downto 0)/2;--"010"; --;
elsif (burst_cnt = "010") then
rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0);
else
rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) - burst_cnt(2 downto 0);
end if;
if(burst_read_state_r3 = '1') then
ctrl_RdEn_r <= '1';
end if;
elsif (rdburst_cnt(2 downto 0) /= "000") then
rdburst_cnt(2 downto 0) <= rdburst_cnt(2 downto 0) - '1';
if(rdburst_cnt = "001") then
ctrl_RdEn_r <= '0';
end if;
else
rdburst_cnt(2 downto 0) <= "000";
end if;
end if;
end process;
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst = '1') then
ctrl_RdEn_r1 <= '0';
else
ctrl_RdEn_r1 <= ctrl_RdEn_r;
end if;
end if;
end process;
ctrl_RdEn <= ctrl_RdEn_r1 when (REGISTERED_VALUE = '1') else
ctrl_RdEn_r;
-- write address FIFO read enable signals
af_rden <= '1' when ((read_write_state = '1') or ((state = MODE_REGISTER_WAIT) and LMR_r = '1' and (mrd_count = '0')) or
((state = PRECHARGE )and PRE_r = '1') or ((state = AUTO_REFRESH) and REF_r = '1')
or ((state = ACTIVE )and ACT_r = '1')) else '0';
-- write data fifo read enable
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst = '1') then
wdf_rden_r <= '0';
elsif (write_state = '1') then -- place holder for burst_write
wdf_rden_r <= '1';
else
wdf_rden_r <= '0';
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst = '1') then
wdf_rden_r2 <= '0';
wdf_rden_r3 <= '0';
wdf_rden_r4 <= '0';
else
wdf_rden_r2 <= wdf_rden_r;
wdf_rden_r3 <= wdf_rden_r2;
wdf_rden_r4 <= wdf_rden_r3;
end if;
end if;
end process;
-- Read enable to the data fifo
process (burst_cnt, wdf_rden_r, wdf_rden_r2, wdf_rden_r3, wdf_rden_r4)
begin
if (burst_cnt = "001") then
ctrl_Wdf_RdEn_r<= (wdf_rden_r ) ;
elsif (burst_cnt = "010") then
ctrl_Wdf_RdEn_r<= (wdf_rden_r or wdf_rden_r2) ;
elsif (burst_cnt = "100") then
ctrl_Wdf_RdEn_r<= (wdf_rden_r or wdf_rden_r2 or wdf_rden_r3 or wdf_rden_r4) ;
else
ctrl_Wdf_RdEn_r<= '0';
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
ctrl_Wdf_RdEn_r1 <= '0';
else
ctrl_Wdf_RdEn_r1 <= ctrl_Wdf_RdEn_r;
end if;
end if;
end process;
ctrl_Wdf_RdEn <= ctrl_Wdf_RdEn_r1 when (REGISTERED_VALUE = '1') else
ctrl_Wdf_RdEn_r;
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
dummy_write_flag <= '0';
else
dummy_write_flag <= phy_Dly_Slct_Done and not(comp_done);
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
init_state <= INIT_IDLE;
else
init_state <= init_next_state;
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
count5 <= (others => '0');
else
case init_state is
when INIT_PRECHARGE_WAIT | INIT_MODE_REGISTER_WAIT | INIT_AUTO_REFRESH_WAIT
| INIT_DUMMY_WRITE_READ | INIT_PATTERN_READ_WAIT | INIT_DUMMY_READ_WAIT | INIT_DUMMY_ACTIVE_WAIT =>
count5 <= count5 + '1';
when others =>
count5 <= (others => '0');
end case;
end if;
end if;
end process;
-- Initialization state machine
process (auto_ref, chip_cnt, count_200cycle_done_r, done_200us,
init_count, init_memory, phy_Dly_Slct_Done, init_state,
burst_cnt, comp_done, dummy_write_flag, REF_r, count5)
begin
init_next_state <= init_state;
case init_state is
when INIT_IDLE =>
if (init_memory = '1' and done_200us = '1') then
case init_count is -- synthesis parallel_case full_case
when "0000" => init_next_state <= INIT_INITCOUNT_200;
when "0001" => init_next_state <= INIT_PRECHARGE;
when "0010" => init_next_state <= INIT_LOAD_MODE_REG_ST;
when "0011" => init_next_state <= INIT_LOAD_MODE_REG_ST;
when "0100" => init_next_state <= INIT_INITCOUNT_200;
when "0101" => init_next_state <= INIT_PRECHARGE;
when "0110" => init_next_state <= INIT_AUTO_REFRESH;
when "0111" => init_next_state <= INIT_AUTO_REFRESH;
when "1000" => init_next_state <= INIT_LOAD_MODE_REG_ST;
when "1001" =>
if( (chip_cnt < no_of_cs-1)) then
init_next_state <= INIT_DEEP_MEMORY_ST;
elsif ((Phy_Mode = '1' and count_200cycle_done_r = '1')) then
init_next_state <= INIT_DUMMY_READ_CYCLES;
else
init_next_state <= INIT_IDLE;
end if;
when "1010" =>
if (phy_Dly_Slct_Done = '1') then
init_next_state <= INIT_IDLE;
end if;
when others => init_next_state <= INIT_IDLE;
end case; -- case(init_count )
end if;
when INIT_DEEP_MEMORY_ST => init_next_state <= INIT_IDLE;
when INIT_INITCOUNT_200 => init_next_state <= INIT_INITCOUNT_200_WAIT;
when INIT_INITCOUNT_200_WAIT =>
if (count_200cycle_done_r = '1') then
init_next_state <= INIT_IDLE;
else
init_next_state <= INIT_INITCOUNT_200_WAIT;
end if;
when INIT_DUMMY_READ_CYCLES => init_next_state <= INIT_DUMMY_ACTIVE;
when INIT_DUMMY_ACTIVE => init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
when INIT_DUMMY_ACTIVE_WAIT =>
if (count5 = cntnext) then
if(dummy_write_flag = '1') then
init_next_state <= INIT_DUMMY_WRITE;
else
init_next_state <= INIT_DUMMY_FIRST_READ;
end if;
else
init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
end if;
when INIT_DUMMY_FIRST_READ =>
init_next_state <= INIT_DUMMY_READ_WAIT;
when INIT_DUMMY_READ =>
if((burst_cnt = "001") and (phy_Dly_Slct_Done = '0')) then
init_next_state <= INIT_DUMMY_READ;
else
init_next_state <= INIT_DUMMY_READ_WAIT;
end if;
when INIT_DUMMY_READ_WAIT =>
if (phy_Dly_Slct_Done = '1') then
if(count5 = cntnext) then
init_next_state <= INIT_PRECHARGE;
else
init_next_state <= INIT_DUMMY_READ_WAIT;
end if;
else
init_next_state <= INIT_DUMMY_READ;
end if;
when INIT_DUMMY_WRITE =>
init_next_state <= INIT_DUMMY_WRITE_READ;
when INIT_DUMMY_WRITE_READ =>
if (count5 = cntnext) then
init_next_state <= INIT_PATTERN_READ;
else
init_next_state <= INIT_DUMMY_WRITE_READ;
end if;
when INIT_PATTERN_READ =>
init_next_state <= INIT_PATTERN_READ_WAIT;
when INIT_PATTERN_READ_WAIT =>
if(comp_done = '1') then
init_next_state <= INIT_PRECHARGE;
else
init_next_state <= INIT_PATTERN_READ_WAIT;
end if;
when INIT_PRECHARGE => init_next_state <= INIT_PRECHARGE_WAIT;
when INIT_PRECHARGE_WAIT =>
if (count5 = cntnext) then
if ((auto_ref or REF_r) = '1') then
init_next_state <= INIT_AUTO_REFRESH;
else
init_next_state <= INIT_IDLE;
end if;
else
init_next_state <= INIT_PRECHARGE_WAIT;
end if;
when INIT_LOAD_MODE_REG_ST => init_next_state <= INIT_MODE_REGISTER_WAIT;
when INIT_MODE_REGISTER_WAIT =>
if (count5 = cntnext) then
init_next_state <= INIT_IDLE;
else
init_next_state <= INIT_MODE_REGISTER_WAIT;
end if;
when INIT_AUTO_REFRESH => init_next_state <= INIT_AUTO_REFRESH_WAIT;
when INIT_AUTO_REFRESH_WAIT =>
if ( (count5 = cntnext) and (phy_Dly_Slct_Done = '1') ) then
init_next_state <= INIT_DUMMY_ACTIVE;
elsif (count5 = cntnext) then
init_next_state <= INIT_IDLE;
else
init_next_state <= INIT_AUTO_REFRESH_WAIT;
end if;
when others => init_next_state <= INIT_IDLE;
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