mem_interface_top_ddr_controller_0.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

  end if;
 end if;
end process;
      
-- rp count
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       rp_count(2 downto 0) <= "000";
   elsif (state = PRECHARGE) then
       rp_count(2 downto 0) <= rp_count_value;
   elsif (rp_count(2 downto 0) /= "000") then
       rp_count(2 downto 0) <= rp_count(2 downto 0) - 1;
   else
     rp_count(2 downto 0) <= "000";
  end if;
 end if;
end process;

-- rfc count
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       rfc_count(5 downto 0) <= "000000";
   elsif (state = AUTO_REFRESH) then
       rfc_count(5 downto 0) <= rfc_count_value;
   elsif (rfc_count(5 downto 0) /= "000000") then
       rfc_count(5 downto 0) <= rfc_count(5 downto 0) - 1;
   else
     rfc_count(5 downto 0) <= "000000";
  end if;
 end if;
end process;
      
-- rcd count - 20ns
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       rcd_count(2 downto 0) <= "000";
   elsif (state = ACTIVE) then
       rcd_count(2 downto 0) <= rcd_count_value;
   elsif (rcd_count(2 downto 0) /= "000") then
       rcd_count(2 downto 0) <= rcd_count(2 downto 0) - 1;
   else
       rcd_count(2 downto 0) <=  "000";
  end if;
 end if;
end process;

     
-- ras count - active to precharge
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       ras_count(3 downto 0) <= "0000";
   elsif (state = ACTIVE) then
       ras_count(3 downto 0) <= ras_count_value;
   elsif (ras_count(3 downto 1) = "000") then
       if (ras_count(0) /= '0') then
              ras_count(0) <= '0';
       end if;
   else
       ras_count(3 downto 0) <= ras_count(3 downto 0) - 1;
  end if;
 end if;
end process;
      
--AL+BL/2+TRTP-2      
-- rtp count - read to precharge
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       rtp_count(3 downto 0) <= "0000";
   elsif (read_state = '1') then
       rtp_count(2 downto 0) <= trtp_count_value ;
   elsif (rtp_count(3 downto 1) = "000") then
       if (rtp_count(0) /= '0') then
              rtp_count(0) <= '0';
       end if;
   else
       rtp_count(3 downto 0) <= rtp_count(3 downto 0) - 1;
  end if;
 end if;
end process;



-- WL+BL/2+TWR      
-- wtp count - write to precharge
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       wtp_count(3 downto 0) <= "0000";
   elsif (write_state = '1') then
       wtp_count(2 downto 0) <= twr_count_value  ;
   elsif (wtp_count(3 downto 1) = "000") then
       if (wtp_count(0) /= '0') then
              wtp_count(0) <= '0';
       end if;
   else
       wtp_count(3 downto 0) <= wtp_count(3 downto 0) - 1;
  end if;
 end if;
end process;


      
-- write to read counter 
      
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       wr_to_rd_count(3 downto 0) <= "0000";
   elsif (write_state = '1') then
       wr_to_rd_count(2 downto 0) <= twtr_count_value;
   elsif (wr_to_rd_count(3 downto 0) /= "0000") then
       wr_to_rd_count(3 downto 0) <= wr_to_rd_count(3 downto 0) - 1;
   else
     wr_to_rd_count(3 downto 0) <= "0000";
  end if;
 end if;
end process;

-- read to write counter
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
      rd_to_wr_count(3 downto 0) <= "0000";
   elsif (read_state = '1') then
      rd_to_wr_count(3 downto 0) <=  registered + burst_cnt + load_mode_reg(6) + load_mode_reg(4);
   elsif (rd_to_wr_count(3 downto 0) /= "0000") then
      rd_to_wr_count(3 downto 0) <= rd_to_wr_count(3 downto 0) - 1;
   else
     rd_to_wr_count(3 downto 0) <= "0000";
  end if;
 end if;
end process;
       

-- auto refresh interval counter in refresh_clk domain
process (refresh_clk)
begin
 if(refresh_clk'event and refresh_clk = '1') then
   if(rst = '1') then
      refi_count <= (others => '0');
   elsif (refi_count = max_ref_cnt ) then
      refi_count <= (others => '0');
   else
      refi_count <= refi_count + 1;
  end if;
 end if;
end process;

 ref_flag <= '1' when ((refi_count = max_ref_cnt) and (done_200us = '1') ) else
	    '0';

--200us counter for cke 
process (refresh_clk) 
begin
 if(refresh_clk'event and refresh_clk = '1') then
  if (rst = '1') then
    cke_200us_cnt <= "11011";
  elsif (refi_count(max_ref_width-1  downto  0) =  max_ref_cnt) then
    cke_200us_cnt  <=  cke_200us_cnt - 1;   
  else  
    cke_200us_cnt  <= cke_200us_cnt;
  end if;
 end if;
end process;


-- refresh detect in 266 MHz clock
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
      ref_flag_266   <= '0';
      ref_flag_266_r <= '0';
      done_200us <= '0';
   else
      ref_flag_266   <= ref_flag;
      ref_flag_266_r <= ref_flag_266;
      if (done_200us = '0' and (cke_200us_cnt = "00000")) then
	done_200us <= '1';
      end if;
  end if;
 end if;
end process;
      
--refresh flag detect
--auto_ref high indicates auto_refresh requirement
--auto_ref is held high until auto refresh command is issued.
process(clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       auto_ref <= '0';
    elsif (ref_flag_266 = '1' and ref_flag_266_r = '0') then
       auto_ref <= '1';
    elsif ((state = AUTO_REFRESH) or (init_state = INIT_AUTO_REFRESH)) then
       auto_ref <= '0';
    else 
       auto_ref <= auto_ref;
  end if;
 end if;
end process;
        
-- 200 clocks counter - count value : C8
-- required for initialization
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       count_200_cycle(7 downto 0) <= "00000000";
   elsif (init_state = INIT_INITCOUNT_200) then
       count_200_cycle(7 downto 0) <= "11001000";
   elsif (count_200_cycle(7 downto 0) /= "00000000") then
       count_200_cycle(7 downto 0) <= count_200_cycle(7 downto 0) - 1;
   else
       count_200_cycle(7 downto 0) <= "00000000";
  end if;
 end if;
end process;

process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       count_200cycle_done_r<= '0';
   elsif ((init_memory = '1') and (count_200_cycle = "00000000")) then
       count_200cycle_done_r<= '1';
   else
       count_200cycle_done_r<= '0';
  end if;
 end if;
end process;
      

process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
      init_done <= '0';
   elsif ((Phy_Mode = '1') and (comp_done ='1') and (count5 = "10100")) then
      init_done <= '1';
   else
      init_done <= init_done;
  end if;
 end if;
end process;
                             
 ctrl_init_done      <= init_done;
                            
 burst_cnt           <= "0010" when (BURST_LENGTH_VALUE = "010") else
                       "0100" when (BURST_LENGTH_VALUE = "011") else
		       "0001";
 burst_cnt_by2	     <= "001" when (BURST_LENGTH_VALUE = "010") else
                       "010" when (BURST_LENGTH_VALUE = "011") else
		       "000";
                                    
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
   if ((rst = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
     init_count(3 downto 0) <= "0000";
  elsif (init_memory = '1') then
     if (init_state = INIT_LOAD_MODE_REG_ST or init_state = INIT_PRECHARGE or init_state = INIT_AUTO_REFRESH or 
         init_state = INIT_DUMMY_READ_CYCLES or init_state = INIT_INITCOUNT_200 or init_state = INIT_DEEP_MEMORY_ST) then
        init_count(3 downto 0) <= init_count(3 downto 0) + 1;
     elsif(init_count = "1010" ) then
        init_count(3 downto 0) <= "0000";   
     else init_count(3 downto 0) <= init_count(3 downto 0);
     end if;
  end if;
 end if;
end process;

process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if ((rst = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
      init_count_cp(3 downto 0) <= "0000";
   elsif (init_memory = '1') then
      if (init_state = INIT_LOAD_MODE_REG_ST or init_state = INIT_PRECHARGE or init_state = INIT_AUTO_REFRESH or 
          init_state = INIT_DUMMY_READ_CYCLES or init_state = INIT_INITCOUNT_200 or init_state = INIT_DEEP_MEMORY_ST) then
         init_count_cp(3 downto 0) <= init_count_cp(3 downto 0) + 1;
      elsif(init_count_cp = "1010" ) then
         init_count_cp(3 downto 0) <= "0000";   
      else init_count_cp(3 downto 0) <= init_count_cp(3 downto 0);
      end if;
  end if;
 end if;
end process;
   
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
        chip_cnt <= "00";
   elsif ( init_state = INIT_DEEP_MEMORY_ST) then
      chip_cnt <= chip_cnt + "01";
   else
      chip_cnt <= chip_cnt;
  end if;
 end if;
end process;

   

-- write burst count
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       wrburst_cnt(2 downto 0) <= "000";
   elsif (write_state = '1' or dummy_write_state = '1') then
       wrburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
   elsif (wrburst_cnt(2 downto 0) /= "000") then
       wrburst_cnt(2 downto 0) <= wrburst_cnt(2 downto 0) - 1;
   else wrburst_cnt(2 downto 0) <= "000";
  end if;
 end if;
end process;

-- read burst count for state machine 
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       read_burst_cnt(2 downto 0) <= "000";
   elsif (read_state = '1') then
       read_burst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
   elsif (read_burst_cnt(2 downto 0) /= "000") then
       read_burst_cnt(2 downto 0) <= read_burst_cnt(2 downto 0) - 1;
   else read_burst_cnt(2 downto 0) <= "000";
  end if;
 end if;
end process;

-- count to generate write enable to the data path
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
       ctrl_WrEn_cnt(2 downto 0) <= "000";
   elsif ((wdf_rden_r = '1') or (dummy_write_state_r = '1')) then
       ctrl_WrEn_cnt(2 downto 0) <= burst_cnt(2 downto 0);
   elsif (ctrl_WrEn_cnt(2 downto 0) /= "000") then
       ctrl_WrEn_cnt(2 downto 0) <= ctrl_WrEn_cnt(2 downto 0) -1;
   else 
       ctrl_WrEn_cnt(2 downto 0) <= "000";
  end if;
 end if;
end process;

--write enable to data path
process (ctrl_WrEn_cnt) 
begin
     if (ctrl_WrEn_cnt(2 downto 0) /= "000") then
        ctrl_WrEn_r <= '1';
     else
        ctrl_WrEn_r <= '0';
     end if;
end process;
    
process(clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
	ctrl_WrEn_r1 <= '0';
    else
	ctrl_WrEn_r1 <= ctrl_WrEn_r;
    end if;
 end if;
end process;

ctrl_WrEn <= ctrl_WrEn_r1 when (REGISTERED_VALUE = '1') else
	     ctrl_WrEn_r;


-- DQS reset to data path
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
      ctrl_Dqs_Rst_r <= '0';
   elsif (first_write_state = '1' or init_state = INIT_DUMMY_WRITE) then
      ctrl_Dqs_Rst_r <= '1';
   else 
      ctrl_Dqs_Rst_r <= '0';
  end if;
 end if;
end process;

process(clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
	ctrl_Dqs_Rst_r1 <= '0';
    else
	ctrl_Dqs_Rst_r1 <= ctrl_Dqs_Rst_r;
    end if;
 end if;
end process;

ctrl_Dqs_Rst <= ctrl_Dqs_Rst_r1 when (REGISTERED_VALUE = '1') else
		ctrl_Dqs_Rst_r;


-- DQS enable to data path
process (clk_0)
begin
 if(clk_0'event and clk_0 = '1') then
    if(rst = '1') then
      ctrl_Dqs_En_r <= '0';
   elsif ((write_state = '1') or (wrburst_cnt /= "000") or (dummy_write_state = '1')) then
      ctrl_Dqs_En_r <= '1';
   else 
      ctrl_Dqs_En_r <= '0';
  end if;
 end if;
end process;