📄 mem_interface_top_ddr_controller_0.vhd
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-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.6
-- \ \ Application : MIG
-- / / Filename: mem_interface_top_ddr_controller_0.vhd
-- /___/ /\ Date Last Modified: Wed Jun 1 2005
-- \ \ / \Date Created: Mon May 2 2005
-- \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: This is the main control logic of the memory interface. All commands
-- are issued from here acoording to the burst, CAS Latency and the
-- user commands.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.mem_interface_top_parameters_0.all;
entity mem_interface_top_ddr_controller_0 is
port(
clk_0 : in std_logic;
refresh_clk : in std_logic;
rst : in std_logic;
-- FIFO signals
af_addr : in std_logic_vector(35 downto 0);
af_empty : in std_logic;
-- signals for the Dummy Reads
comp_done : in std_logic;
phy_Dly_Slct_Done : in std_logic;
ctrl_Dummyread_Start : out std_logic;
-- FIFO read enable signals
ctrl_af_RdEn : out std_logic;
ctrl_Wdf_RdEn : out std_logic;
-- Rst and Enable signals for DQS logic
ctrl_Dqs_Rst : out std_logic;
ctrl_Dqs_En : out std_logic;
-- Read and Write Enable signals to the phy interface
ctrl_WrEn : out std_logic;
ctrl_RdEn : out std_logic;
--
ctrl_ddr_address : out std_logic_vector((row_address - 1) downto 0);
ctrl_ddr_ba : out std_logic_vector((bank_address - 1) downto 0);
ctrl_ddr_ras_L : out std_logic;
ctrl_ddr_cas_L : out std_logic;
ctrl_ddr_we_L : out std_logic;
ctrl_ddr_cs_L : out std_logic;
ctrl_ddr_cke : out std_logic;
dummy_write_pattern : out std_logic;
burst_length : out std_logic_vector(2 downto 0)
);
end mem_interface_top_ddr_controller_0;
architecture arch of mem_interface_top_ddr_controller_0 is
signal init_count : std_logic_vector(3 downto 0);
signal init_count_cp : std_logic_vector(3 downto 0);
signal init_memory : std_logic;
signal count_200_cycle : std_logic_vector(7 downto 0);
signal ref_flag : std_logic;
signal ref_flag_266 : std_logic;
signal ref_flag_266_r : std_logic;
signal auto_ref : std_logic;
signal next_state : std_logic_vector(4 downto 0);
signal state : std_logic_vector(4 downto 0);
signal state_r2 : std_logic_vector(4 downto 0);
signal state_r3 : std_logic_vector(4 downto 0);
signal row_addr_r : std_logic_vector((row_address - 1) downto 0);
signal ddr_address_init_r : std_logic_vector((row_address - 1) downto 0);
signal ddr_address_r1 : std_logic_vector((row_address - 1) downto 0);
signal ddr_ba_r1 : std_logic_vector((bank_address - 1) downto 0);
signal mrd_count : std_logic;
signal rp_count : std_logic_vector(2 downto 0);
signal rfc_count : std_logic_vector(5 downto 0);
signal rcd_count : std_logic_vector(2 downto 0);
signal ras_count : std_logic_vector(3 downto 0);
signal wr_to_rd_count : std_logic_vector(3 downto 0);
signal rd_to_wr_count : std_logic_vector(3 downto 0);
signal rtp_count : std_logic_vector(3 downto 0);
signal wtp_count : std_logic_vector(3 downto 0);
signal refi_count : std_logic_vector((max_ref_width - 1) downto 0);
signal cas_count : std_logic_vector(2 downto 0);
signal cas_check_count : std_logic_vector(3 downto 0);
signal wrburst_cnt : std_logic_vector(2 downto 0);
signal read_burst_cnt : std_logic_vector(2 downto 0);
signal ctrl_WrEn_cnt : std_logic_vector(2 downto 0);
signal rdburst_cnt : std_logic_vector(2 downto 0);
signal af_addr_r : std_logic_vector(35 downto 0);
signal af_addr_r1 : std_logic_vector(35 downto 0);
signal wdf_rden_r : std_logic;
signal wdf_rden_r2 : std_logic;
signal wdf_rden_r3 : std_logic;
signal wdf_rden_r4 : std_logic;
signal af_rden : std_logic;
signal ddr_ras_r2 : std_logic;
signal ddr_cas_r2 : std_logic;
signal ddr_we_r2 : std_logic;
signal ddr_ras_r : std_logic;
signal ddr_cas_r : std_logic;
signal ddr_we_r : std_logic;
signal ddr_ras_r3 : std_logic;
signal ddr_cas_r3 : std_logic;
signal ddr_we_r3 : std_logic;
signal idle_cnt : std_logic_vector(3 downto 0);
signal ctrl_Dummyread_Start_r1 : std_logic;
signal ctrl_Dummyread_Start_r2 : std_logic;
signal ctrl_Dummyread_Start_r3 : std_logic;
signal ctrl_Dummyread_Start_r4 : std_logic;
signal conflict_resolved_r : std_logic;
signal ddr_cke_r : std_logic;
signal chip_cnt : std_logic_vector(1 downto 0);
signal dummy_read_en : std_logic;
signal ctrl_init_done : std_logic;
signal count_200cycle_done_r : std_logic;
signal init_done : std_logic;
signal burst_cnt : std_logic_vector(3 downto 0);
signal burst_cnt_by2 : std_logic_vector(2 downto 0);
signal conflict_detect : std_logic;
signal conflict_detect_r : std_logic;
signal load_mode_reg : std_logic_vector((row_address - 1) downto 0);
signal ext_mode_reg : std_logic_vector((row_address - 1) downto 0);
signal CAS_LATENCY_VALUE : std_logic_vector(3 downto 0);
signal BURST_LENGTH_VALUE : std_logic_vector(2 downto 0);
signal REGISTERED_VALUE : std_logic;
signal ECC_VALUE : std_logic;
signal WR : std_logic;
signal RD : std_logic;
signal LMR : std_logic;
signal PRE : std_logic;
signal REF : std_logic;
signal ACT : std_logic;
signal WR_r : std_logic;
signal RD_r : std_logic;
signal LMR_r : std_logic;
signal PRE_r : std_logic;
signal REF_r : std_logic;
signal ACT_r : std_logic;
signal af_empty_r : std_logic;
signal LMR_PRE_REF_ACT_cmd_r : std_logic;
signal command_address : std_logic_vector(2 downto 0);
signal zeroes : std_logic_vector((row_address - col_ap_width) downto 0);
signal cke_200us_cnt : std_logic_vector(4 downto 0);
signal done_200us : std_logic;
signal write_state : std_logic;
signal read_state : std_logic;
signal read_write_state : std_logic;
signal burst_write_state : std_logic;
signal first_write_state : std_logic;
signal burst_read_state : std_logic;
signal first_read_state : std_logic;
signal burst_read_state_r2 : std_logic;
signal burst_read_state_r3 : std_logic;
signal first_read_state_r2 : std_logic;
signal read_write_state_r2 : std_logic;
signal read_write_state_r3 : std_logic;
signal dummy_write_state : std_logic;
signal dummy_write_state_r : std_logic;
signal pattern_read_state : std_logic;
signal pattern_read_state_r2 : std_logic;
signal pattern_read_state_r3 : std_logic;
signal dummy_write_flag : std_logic;
constant IDLE : std_logic_vector(4 downto 0) := "00000";-- 5'h00
constant LOAD_MODE_REG_ST : std_logic_vector(4 downto 0) := "00001";-- 5'h01
constant MODE_REGISTER_WAIT : std_logic_vector(4 downto 0) := "00010";-- 5'h02
constant PRECHARGE : std_logic_vector(4 downto 0) := "00011";-- 5'h03
constant PRECHARGE_WAIT : std_logic_vector(4 downto 0) := "00100";-- 5'h04
constant AUTO_REFRESH : std_logic_vector(4 downto 0) := "00101";-- 5'h05
constant AUTO_REFRESH_WAIT : std_logic_vector(4 downto 0) := "00110";-- 5'h06
constant ACTIVE : std_logic_vector(4 downto 0) := "00111";-- 5'h07
constant ACTIVE_WAIT : std_logic_vector(4 downto 0) := "01000";-- 5'h08
constant FIRST_WRITE : std_logic_vector(4 downto 0) := "01001";-- 5'h09
constant BURST_WRITE : std_logic_vector(4 downto 0) := "01010";-- 5'h0A
constant WRITE_WAIT : std_logic_vector(4 downto 0) := "01011";-- 5'h0B
constant WRITE_READ : std_logic_vector(4 downto 0) := "01100";-- 5'h0C
constant FIRST_READ : std_logic_vector(4 downto 0) := "01101";-- 5'h0D
constant BURST_READ : std_logic_vector(4 downto 0) := "01110";-- 5'h0E
constant READ_WAIT : std_logic_vector(4 downto 0) := "01111";-- 5'h0F
constant READ_WRITE : std_logic_vector(4 downto 0) := "10000";-- 5'h10
constant INIT_IDLE : std_logic_vector(4 downto 0) := "00000";-- 5'h01
constant INIT_DEEP_MEMORY_ST : std_logic_vector(4 downto 0) := "00001";-- 5'h02
constant INIT_INITCOUNT_200 : std_logic_vector(4 downto 0) := "00010";-- 5'h03
constant INIT_INITCOUNT_200_WAIT : std_logic_vector(4 downto 0) := "00011";-- 5'h04
constant INIT_DUMMY_READ_CYCLES : std_logic_vector(4 downto 0) := "00100";-- 5'h05
constant INIT_DUMMY_ACTIVE : std_logic_vector(4 downto 0) := "00101";-- 5'h06
constant INIT_DUMMY_ACTIVE_WAIT : std_logic_vector(4 downto 0) := "00110";-- 5'h07
constant INIT_DUMMY_FIRST_READ : std_logic_vector(4 downto 0) := "00111";-- 5'h08
constant INIT_DUMMY_READ : std_logic_vector(4 downto 0) := "01000";-- 5'h09
constant INIT_DUMMY_READ_WAIT : std_logic_vector(4 downto 0) := "01001";-- 5'h0A
constant INIT_DUMMY_WRITE : std_logic_vector(4 downto 0) := "01010";-- 5'h0B
constant INIT_DUMMY_WRITE_READ : std_logic_vector(4 downto 0) := "01011";-- 5'h0C
constant INIT_PATTERN_READ : std_logic_vector(4 downto 0) := "01100";-- 5'h0D
constant INIT_PATTERN_READ_WAIT : std_logic_vector(4 downto 0) := "01101";-- 5'h0E
constant INIT_PRECHARGE : std_logic_vector(4 downto 0) := "01110";-- 5'h0F
constant INIT_PRECHARGE_WAIT : std_logic_vector(4 downto 0) := "01111";-- 5'h10
constant INIT_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10000";-- 5'h11
constant INIT_AUTO_REFRESH_WAIT : std_logic_vector(4 downto 0) := "10001";-- 5'h12
constant INIT_LOAD_MODE_REG_ST : std_logic_vector(4 downto 0) := "10010";-- 5'h13
constant INIT_MODE_REGISTER_WAIT : std_logic_vector(4 downto 0) := "10011";-- 5'h14
signal ctrl_Wdf_RdEn_r : std_logic;
signal ctrl_Wdf_RdEn_r1 : std_logic;
signal ctrl_Dqs_Rst_r : std_logic;
signal ctrl_Dqs_Rst_r1 : std_logic;
signal ctrl_WrEn_r : std_logic;
signal ctrl_WrEn_r1 : std_logic;
signal ctrl_RdEn_r : std_logic;
signal ctrl_RdEn_r1 : std_logic;
signal ctrl_Dqs_En_r : std_logic;
signal ctrl_Dqs_En_r1 : std_logic;
signal dummy_write_pattern_1 : std_logic;
signal dummy_write_pattern_2 : std_logic;
signal ddr_address_r2 : std_logic_vector((row_address - 1) downto 0);
signal ddr_ba_r2 : std_logic_vector((bank_address - 1) downto 0);
signal init_next_state : std_logic_vector(4 downto 0);
signal init_state : std_logic_vector(4 downto 0);
signal init_state_r2 : std_logic_vector(4 downto 0);
signal init_state_r3 : std_logic_vector(4 downto 0);
signal count5 : std_logic_vector(4 downto 0);
constant cntnext : std_logic_vector(4 downto 0) := "11000";
begin
REGISTERED_VALUE <= '0';
CAS_LATENCY_VALUE <= "0010" when (load_mode_reg(6 downto 4) = "110") else
'0' & load_mode_reg(6 downto 4) ;
BURST_LENGTH_VALUE <= load_mode_reg(2 downto 0);
burst_length <= burst_cnt(2 downto 0);
command_address <= af_addr(34 downto 32);
zeroes <= (others => '0');
ECC_VALUE <= ecc_enable;
burst_read_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = BURST_READ) and (RD = '1') else '0';
first_read_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = FIRST_READ) and (RD = '1') else '0';
read_state <= burst_read_state or first_read_state;
read_write_state <= write_state or read_state;
burst_write_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = BURST_WRITE) and (WR = '1') else '0';
first_write_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = FIRST_WRITE) and (WR = '1') else '0';
write_state <= burst_write_state or first_write_state;
dummy_write_state <= '1' when (init_state = INIT_DUMMY_WRITE) else '0';
dummy_write_pattern_1 <= '1' when ((init_state = INIT_DUMMY_WRITE) or (init_state = INIT_DUMMY_WRITE_READ)) else '0';
pattern_read_state <= '1' when (init_state = INIT_PATTERN_READ) else '0';
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
dummy_write_pattern_2 <= '0';
else
dummy_write_pattern_2 <= dummy_write_pattern_1;
end if;
end if;
end process;
dummy_write_pattern <= dummy_write_pattern_2 when (REGISTERED_VALUE = '1') else dummy_write_pattern_1;
-- fifo control signals
ctrl_af_RdEn <= af_rden;
conflict_detect <= af_addr(35) and ctrl_init_done and (not af_empty);
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
pattern_read_state_r2 <= '0';
pattern_read_state_r3 <= '0';
else
pattern_read_state_r2 <= pattern_read_state;
pattern_read_state_r3 <= pattern_read_state_r2;
end if;
end if;
end process;
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
dummy_write_state_r <= '0';
else
dummy_write_state_r <= dummy_write_state;
end if;
end if;
end process;
--commands
process(command_address, ctrl_init_done, af_empty)
begin
WR <= '0';
RD <= '0';
LMR <= '0';
PRE <= '0';
REF <= '0';
ACT <= '0';
if((ctrl_init_done = '1') and (af_empty = '0')) then
case command_address is
when "000" => LMR <= '1';
when "001" => REF <= '1';
when "010" => PRE <= '1';
when "011" => ACT <= '1';
when "100" => WR <= '1';
when "101" => RD <= '1';
when others => null;
end case;
end if;
end process;
-- register address outputs
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
WR_r <= '0';
RD_r <= '0';
LMR_r <= '0';
PRE_r <= '0';
REF_r <= '0';
ACT_r <= '0';
af_empty_r <= '0';
LMR_PRE_REF_ACT_cmd_r <= '0';
else
WR_r <= WR;
RD_r <= RD;
LMR_r <= LMR;
PRE_r <= PRE;
REF_r <= REF;
ACT_r <= ACT;
LMR_PRE_REF_ACT_cmd_r <= LMR or PRE or REF or ACT;
af_empty_r <= af_empty;
end if;
end if;
end process;
-- register address outputs
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
af_addr_r <= (others => '0');
af_addr_r1 <= (others => '0');
conflict_detect_r <= '0';
read_write_state_r2 <= '0';
read_write_state_r3 <= '0';
first_read_state_r2 <= '0';
burst_read_state_r2 <= '0';
burst_read_state_r3 <= '0';
else
af_addr_r <= af_addr;
af_addr_r1 <= af_addr_r;
conflict_detect_r <= conflict_detect;
read_write_state_r2 <= read_write_state;
read_write_state_r3 <= read_write_state_r2;
first_read_state_r2 <= first_read_state;
burst_read_state_r2 <= burst_read_state;
burst_read_state_r3 <= burst_read_state_r2;
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
load_mode_reg <= load_mode_register((row_address-1) downto 0);
elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and (LMR_r = '1') and (af_addr_r((bank_address+row_address + col_ap_width -1) downto (col_ap_width + row_address))="00")) then
load_mode_reg <= af_addr ((row_address-1) downto 0);
end if;
end if;
end process;
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
ext_mode_reg <= ext_load_mode_register((row_address-1) downto 0);
elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and (LMR_r = '1') and (af_addr_r((bank_address+row_address + col_ap_width -1) downto (col_ap_width + row_address))= "01")) then
ext_mode_reg <= af_addr (row_address-1 downto 0);
end if;
end if;
end process;
--to initialize memory
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if ((rst = '1') or (init_state = INIT_DEEP_MEMORY_ST)) then
init_memory <= '1';
elsif (init_count_cp = "1010") then
init_memory <= '0';
else
init_memory <= init_memory;
end if;
end if;
end process;
-- mrd count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst = '1') then
mrd_count <= '0';
elsif (state = LOAD_MODE_REG_ST) then
mrd_count <= mrd_count_value;
elsif (mrd_count /= '0') then
mrd_count <= '0';
else
mrd_count <= '0';
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