mem_interface_top_main_0.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_main_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: The main design logic is instantiated here which includes the test 
--		bench and the user interface also. It takes the memory signals and the calibrated
--		clocks and the reset signals from the DCM.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.mem_interface_top_parameters_0.all;

entity mem_interface_top_main_0 is
	port( clk_0             : in std_logic;
	      clk_90            : in std_logic;
	      clk_50            : in std_logic;
	      ref_clk           : in std_logic;
	      idelay_ctrl_rdy   : in std_logic;
	      sys_rst_ref_clk_1 : in std_logic;
	      sys_rst		: in std_logic;
	      sys_rst90		: in std_logic;
	      DDR_CK            : out std_logic_vector((clk_width-1) downto 0);
	      DDR_CK_N          : out std_logic_vector((clk_width-1) downto 0);
	      DDR_RAS_N         : out std_logic;
	      DDR_CAS_N         : out std_logic;
	      DDR_WE_N          : out std_logic;
	      DDR_BA            : out std_logic_vector((bank_address-1) downto 0);
	      DDR_A             : out std_logic_vector((row_address-1) downto 0);
	      DDR_DQ            : inout std_logic_vector((data_width-1) downto 0);
	      DDR_DQS           : inout std_logic_vector((data_strobe_width-1) downto 0);
	      
	      DDR_DM            : out std_logic_vector((data_mask_width-1) downto 0);

	      

	      DDR_CKE           : out std_logic;
	      DDR_CS_N          : out std_logic;
	      ERROR             : out std_logic
	    );
end mem_interface_top_main_0;

architecture arch of mem_interface_top_main_0 is

component mem_interface_top_top_0
	port( clk_0             : in std_logic;
	      clk_90            : in std_logic;
	      clk_50            : in std_logic;
	      ref_clk           : in std_logic;
	      idelay_ctrl_rdy   : in std_logic;
	      sys_rst_ref_clk_1 : in std_logic;
	      sys_rst		: in std_logic;
	      sys_rst90		: in std_logic;
	     
	      DDR_RAS_N              : out std_logic;  
	      DDR_CAS_N              : out std_logic;  
	      DDR_WE_N               : out std_logic;  
	      DDR_CKE                : out std_logic; 
	      DDR_CS_N               : out std_logic; 
	      DDR_DQ                 : inout std_logic_vector((data_width-1) downto 0);        
	      DDR_DQS                : inout std_logic_vector((data_strobe_width-1) downto 0); 
	      
	      DDR_DM                 : out std_logic_vector((data_mask_width-1) downto 0); 
	      APP_MASK_DATA          : in std_logic_vector((data_mask_width*2 -1) downto 0); 
 
	      
	      DDR_CK                 : out std_logic_vector((clk_width-1) downto 0);  
	      DDR_CK_N               : out std_logic_vector((clk_width-1) downto 0);  
	      DDR_BA                 : out std_logic_vector((bank_address-1) downto 0);  
	      DDR_A                  : out std_logic_vector((row_address-1) downto 0);   
	      WDF_ALMOST_FULL        : out std_logic;  
	      AF_ALMOST_FULL         : out std_logic;  
	      BURST_LENGTH           : out std_logic_vector(2 downto 0); 
	      READ_DATA_VALID        : out std_logic;   
	      READ_DATA_FIFO_OUT     : out std_logic_vector((data_width*2 -1) downto 0);  
	      APP_AF_ADDR            : in std_logic_vector(35 downto 0); 
	      APP_AF_WREN            : in std_logic; 
	      APP_WDF_DATA           : in std_logic_vector((data_width*2 -1) downto 0); 
	      APP_WDF_WREN           : in std_logic;  
	      CLK_TB                 : out std_logic;   
	      RESET_TB               : out std_logic
	    );
end component;

component mem_interface_top_test_bench_0
	port( CLK                 : in std_logic;
	      RESET               : in std_logic;
	      WDF_ALMOST_FULL     : in std_logic;
	      AF_ALMOST_FULL      : in std_logic;
	      BURST_LENGTH        : in std_logic_vector(2 downto 0);
	      READ_DATA_VALID     : in std_logic;
	      READ_DATA_FIFO_OUT  : in std_logic_vector((data_width*2 -1) downto 0);
	      APP_AF_ADDR         : out std_logic_vector(35 downto 0);
	      APP_AF_WREN         : out std_logic;
	      APP_WDF_DATA        : out std_logic_vector((data_width*2 -1) downto 0);
	      APP_MASK_DATA       : out std_logic_vector((data_mask_width*2 -1) downto 0);
	      APP_WDF_WREN        : out std_logic;
	      ERROR               : out std_logic 
	    );
end component;

signal app_af_addr	: std_logic_vector(35 downto 0);
signal app_af_wren	: std_logic;
signal app_wr_df_data	: std_logic_vector((data_width*2 -1) downto 0);
signal app_mask_df_data  : std_logic_vector((data_mask_width*2 -1) downto 0);
signal app_wr_df_wren	: std_logic;
signal wr_df_almost_full: std_logic;
signal rd_data_valid	: std_logic;
signal rd_data_fifo_out	: std_logic_vector((data_width*2 -1) downto 0);
signal burst_length	: std_logic_vector(2 downto 0);
signal clk_tb		: std_logic;
signal reset_tb		: std_logic;
signal af_almost_full	: std_logic;

begin


top_00: mem_interface_top_top_0 port map
	( clk_0                 => clk_0,                
	  clk_90                => clk_90,               
	  clk_50                => clk_50,               
	  ref_clk               => ref_clk,  
	  
          sys_rst_ref_clk_1	=> sys_rst_ref_clk_1,
	  sys_rst		=> sys_rst,
	  sys_rst90		=> sys_rst90,
	   
          
	  idelay_ctrl_rdy       => idelay_ctrl_rdy,      
	  DDR_RAS_N             => DDR_RAS_N,            
	  DDR_CAS_N             => DDR_CAS_N,            
	  DDR_WE_N              => DDR_WE_N,             
	  DDR_CKE               => DDR_CKE,              
	  DDR_CS_N              => DDR_CS_N,             
	  DDR_DQ                => DDR_DQ,               
	  DDR_DQS               => DDR_DQS,              
	  
	  DDR_DM                => DDR_DM,               
	  APP_MASK_DATA         => app_mask_df_data,        

	  
	  DDR_CK                => DDR_CK,               
	  DDR_CK_N              => DDR_CK_N,             
	  DDR_BA                => DDR_BA,               
	  DDR_A                 => DDR_A,               
	  WDF_ALMOST_FULL       => wr_df_almost_full,      
	  AF_ALMOST_FULL        => af_almost_full,       
	  BURST_LENGTH          => burst_length,         
	  READ_DATA_VALID       => rd_data_valid,      
	  READ_DATA_FIFO_OUT    => rd_data_fifo_out,   
	  APP_AF_ADDR           => app_af_addr,          
	  APP_AF_WREN           => app_af_wren,          
	  APP_WDF_DATA          => app_wr_df_data,         
	  APP_WDF_WREN          => app_wr_df_wren,         
	  CLK_TB                => clk_tb,               
	  RESET_TB              => reset_tb
	);

test_bench_00: 	mem_interface_top_test_bench_0 port map
	    ( CLK                 => clk_tb,
	      RESET               => reset_tb,
	      WDF_ALMOST_FULL     => wr_df_almost_full,
	      AF_ALMOST_FULL      => af_almost_full,
	      BURST_LENGTH        => burst_length,
	      READ_DATA_VALID     => rd_data_valid,
	      READ_DATA_FIFO_OUT  => rd_data_fifo_out,
	      APP_AF_ADDR         => app_af_addr,
	      APP_AF_WREN         => app_af_wren,
	      APP_WDF_DATA        => app_wr_df_data,
	      APP_MASK_DATA       => app_mask_df_data,
	      APP_WDF_WREN        => app_wr_df_wren,
	      ERROR               => ERROR
	    );	

end arch;