altera_avalon_checksum.vhd

de2 avalon checksum by vhdl

--/****************************************************************************
--*                                                                             *
--* License Agreement                                                           *
--*                                                                             *
--* Copyright (c) 2007 Altera Corporation, San Jose, California, USA.           *
--* All rights reserved.                                                        *
--* This agreement shall be governed in all respects by the laws of the State   *
--* of California and by the laws of the United States of America.              *
--*                                                                             *
--******************************************************************************/
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

-- Top-level module
ENTITY altera_avalon_checksum IS

	--////Global Avalon interface siganals    
	--GENERIC ( n : INTEGER := 32 ) ;
	PORT ( 
		--//Signals for Avalon-MM slave port
		gls_clk, gls_reset_n : in std_logic;
		
		--Signals for Avalon-MM slave port		
		avs_s1_address :in std_logic_vector(2 DOWNTO 0) := "000";
				
		avs_s1_chipselect_n : in std_logic;
		avs_s1_read_n : in std_logic;
		avs_s1_write_n : in std_logic;
		avs_s1_writedata :in std_logic_vector(31 DOWNTO 0) := x"0000_0000";
		
		avs_s1_readdata : out std_logic_vector(31 DOWNTO 0) := x"0000_0000";
		
		--Signals for read only Avalon-MM master port
		avm_m1_address : out std_logic_vector(31 DOWNTO 0) := x"0000_0000";
		avm_m1_byteenable : out std_logic_vector(3 DOWNTO 0) := "0000";
		avm_m1_read_n : out std_logic;
		avm_m1_readdata : in std_logic_vector(31 DOWNTO 0) := x"0000_0000";
		avm_m1_waitrequest: in std_logic
		
		);
		
END altera_avalon_checksum;


--// Module contents
ARCHITECTURE Behavior OF altera_avalon_checksum IS
	

	component read_master
		--GENERIC ( n : INTEGER := 32 ) ;
		PORT ( 
			--//Signals for Avalon-MM slave port
			gls_clk, gls_reset_n : in std_logic;
			
			--Signals for Avalon-MM master port		
			avm_m1_address :out std_logic_vector(31 DOWNTO 0) := x"0000_0000";
			
			--for future byte lane control 
			avm_m1_byteenable	:out std_logic_vector(3 DOWNTO 0);
			avm_m1_read_n :out std_logic;
			avm_m1_readdata : in std_logic_vector(31 DOWNTO 0);
			avm_m1_waitrequest :in std_logic;
			
			addr_reg : in STD_LOGIC_VECTOR(31 DOWNTO 0);
			len_reg : in STD_LOGIC_VECTOR(15 DOWNTO 0);
			go : in std_logic;
			
			avm_m1_byteenable_mask:out std_logic_vector(3 DOWNTO 0);  -- debug - for byteenable mask values		
			read_busy :out std_logic;    -- busy bit
			data_in_ready :out std_logic; 
			count :out std_logic_vector(15 DOWNTO 0); 		-- debug - check count value and for future enhancement
			data_to_process  :out std_logic_vector(31 DOWNTO 0)
			
			);
	end component;
		--signal bcd1n:std_logic_vector(3 downto 0):="0000";
	component s1_slave		
		--GENERIC ( n : INTEGER := 32 ) ;
		PORT ( 
			--//Signals for Avalon-MM slave port
			gls_clk, gls_reset_n : in std_logic;		
			avs_s1_address :in std_logic_vector(2 DOWNTO 0);
			avs_s1_read_n, avs_s1_write_n :in std_logic;
			avs_s1_writedata :in std_logic_vector(31 DOWNTO 0);
			avs_s1_readdata : out std_logic_vector(31 DOWNTO 0);
			avs_s1_chipselect_n :in std_logic;
			
			--//Signals Avalon-MM master module
			addr_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
			len_reg : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			go : out std_logic;
			read_busy :in std_logic;    --// busy bit
			edge_pulse : out std_logic;  --// debug -- look for busy bit transition
			--// Signals transform
			result :in std_logic_vector(15 DOWNTO 0)
		);
	end component;

	component checksum_task_logic 
		--GENERIC ( n : INTEGER := 32 ) ;
		PORT (  data_to_process  	: IN STD_LOGIC_VECTOR(31 DOWNTO 0) ;
				gls_clk, gls_reset_n, go, data_in_ready : IN STD_LOGIC ;			
				result: out STD_LOGIC_VECTOR(15 DOWNTO 0)
				);
	end component;
--	========================
--	========================

--signal gls_clk: STD_LOGIC;
signal go: STD_LOGIC;
signal data_to_process: STD_LOGIC_VECTOR (31 downto 0);
signal result: STD_LOGIC_VECTOR (15 downto 0);

---------------------------------
       --SIGNAL avm_m1_address_xhdl1     :  std_logic_vector(31 DOWNTO 0);   
       -- Check for valid read data on the master port by looking for waitrequest with each read
       --wire [31:0] address = addr;
       SIGNAL addr_reg                :  std_logic_vector(31 DOWNTO 0);   
       SIGNAL len_reg  :  std_logic_vector(15 DOWNTO 0);   
       SIGNAL avm_m1_byteenable_mask    :  std_logic_vector(3 DOWNTO 0);   
       SIGNAL read_busy          :  std_logic;   
       SIGNAL data_in_ready              :  std_logic;   
			 signal count: STD_LOGIC_VECTOR (15 downto 0);
       --SIGNAL data_to_process    :  std_logic_vector(31 DOWNTO 0);   
		 signal edge_pulse: STD_LOGIC;
	
--	=======================
begin

	do_read : read_master port map (
		gls_clk => gls_clk, gls_reset_n=>gls_reset_n,
		avm_m1_address =>avm_m1_address,
		avm_m1_byteenable=>avm_m1_byteenable,
	 avm_m1_read_n=>avm_m1_read_n,
	 avm_m1_readdata=>avm_m1_readdata,
	 avm_m1_waitrequest=>avm_m1_waitrequest,
	 addr_reg=>addr_reg,
	 len_reg =>len_reg,
	 go=>go,
	 avm_m1_byteenable_mask=>avm_m1_byteenable_mask, 
	 read_busy=>read_busy,
	 data_in_ready=>data_in_ready,
	 count =>count,
	 data_to_process => data_to_process
 
	);
	-- Instantiate the Unit Under Test (UUT)
	chk: checksum_task_logic
	    PORT MAP(
	    data_to_process =>data_to_process,
	    gls_clk => gls_clk, gls_reset_n=>gls_reset_n,
	    go=> go,	    
			data_in_ready => data_in_ready,
			result => result			
		);
	--
	ss: s1_slave PORT MAP (
	    gls_clk => gls_clk, gls_reset_n=>gls_reset_n,
              avs_s1_address => avs_s1_address,
              avs_s1_read_n =>  avs_s1_read_n,
              avs_s1_write_n=>   avs_s1_write_n, 
              avs_s1_writedata => avs_s1_writedata,
              avs_s1_readdata => avs_s1_readdata,
              avs_s1_chipselect_n => avs_s1_chipselect_n,   
              addr_reg=> addr_reg  ,
              len_reg => len_reg, 
              go =>go,             
              read_busy  => read_busy ,            
              edge_pulse => edge_pulse ,   
              result =>  result
              );

END behavior;