checksum_task_logic.vhd

de2 avalon checksum by vhdl

LIBRARY ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Top-level module
ENTITY checksum_task_logic IS
	--GENERIC ( n : INTEGER := 32 ) ;
	PORT (  data_to_process  	: IN STD_LOGIC_VECTOR(31 DOWNTO 0) ;
			gls_clk, gls_reset_n, go, data_in_ready : IN STD_LOGIC ;			
			result: out STD_LOGIC_VECTOR(15 DOWNTO 0)
			);
END checksum_task_logic;

ARCHITECTURE behavior OF checksum_task_logic IS

-- define a temparary signal to store the result
signal  data_in_reg, sum_reg: std_logic_vector(31 downto 0);
signal data_in_ready_delay : STD_LOGIC;

signal  sum_1 :std_logic_vector(31 downto 0) :=x"0000_0000";
signal  sum_2, sum_3, next_sum_reg :std_logic_vector(31 downto 0) :=x"0000_0000";
--signal  t1, t2 :std_logic_vector(31 downto 0) :=x"0000_0000";
BEGIN
	-- concurrent statement
	--process(gls_clk)
	--begin
	--variable  sum_1: integer; --failse;
	--end process;
	
	--sum_1(31 downto 0) <= ((x"0000_ffff" & data_in_reg(15 downto 0))+ ( data_in_reg(31 downto 16) ));
	--sum_1(31 downto 0) sll 16; fail
	-- ok too-- sum_1(19 downto 0) <= ( (x"0_0000" + data_in_reg(15 downto 0))+ ( data_in_reg(31 downto 16) ));
	
	--the result is ok, but wrong express, as below. 
	--sum_1(19 downto 0) <= ( (x"0_0000" + data_in_reg(31 downto 16))+ ( data_in_reg(15 downto 0) ));
	--&  is Concatenation
	sum_1 <= ( (x"0000" & data_in_reg(31 downto 16))+ ( data_in_reg(15 downto 0) ));

	--t1(31 downto 0) <= ((x"0000_ffff" )and data_in_reg(15 downto 0) ) ;
	
	next_sum_reg <= sum_1 + sum_reg ;
	--sum_2 (31 downto 0)<= sum_reg(31 downto 16) + sum_reg(15 downto 0);
	sum_2 <= ( (x"0000" & sum_reg(15 downto 0) + sum_reg(31 downto 16) ));	
	sum_3 <= ( (x"0000" & sum_2(31 downto 16)+ sum_2(15 downto 0) ));
	result <=  not (sum_3(15 downto 0)) ;
	
	
	
	process(gls_clk)
	begin
		if( gls_reset_n = '0')	then
				data_in_ready_delay <= '0';
		elsif( gls_clk' event and gls_clk = '1' ) then
				data_in_ready_delay <= data_in_ready;
		end if;
	end process;

	process(gls_clk)
	begin
		if( gls_reset_n = '0')	then
				data_in_reg <= x"0000_0000";
		elsif( gls_clk' event and gls_clk = '1' ) then
				data_in_reg <= data_to_process;
		end if;
	end process;
	
	process(gls_clk)
	begin
		if( gls_reset_n = '0') then				
				sum_reg <= x"0000_0000";		
		elsif (gls_clk' event and gls_clk= '1') then			
		
			if( go ='1' )then
				sum_reg <= x"0000_0000";
			elsif( data_in_ready_delay = '1')  then
				sum_reg <= next_sum_reg;
			else
				sum_reg <= sum_reg;
			end if;
			
		end if;	
	end process;

END behavior;