read_master.vhd

de2 avalon checksum by vhdl

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--
-- VHDL file generated by X-HDL - Revision 3.2.37  Dec. 3, 2003 
-- Thu Jun 19 12:34:43 2008
--
--      Input file         : E:/DE2_WEB/altera_avalon_checksum/hdl/read_master.v
--      Design name        : read_master
--      Author             : 
--      Company            : 
--
--      Description        : 
--
--
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--
--*****************************************************************************
-- *****************************************************************************
-- *                                                                             *
-- * License Agreement                                                           *
-- *                                                                             *
-- * Copyright (c) 2007 Altera Corporation, San Jose, California, USA.           *
-- * All rights reserved.                                                        *
-- *                                                                             *
-- * Permission is hereby granted, free of charge, to any person obtaining a     *
-- * copy of this software and associated documentation files (the "Software"),  *
-- * to deal in the Software without restriction, including without limitation   *
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-- * and/or sell copies of the Software, and to permit persons to whom the       *
-- * Software is furnished to do so, subject to the following conditions:        *
-- *                                                                             *
-- * The above copyright notice and this permission notice shall be included in  *
-- * all copies or substantial portions of the Software.                         *
-- *                                                                             *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-- * DEALINGS IN THE SOFTWARE.                                                   *
-- *                                                                             *
-- * This agreement shall be governed in all respects by the laws of the State   *
-- * of California and by the laws of the United States of America.              *
-- *                                                                             *
-- *****************************************************************************
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

ENTITY read_master IS
       PORT (
              gls_clk                 : IN std_logic;   
              gls_reset_n             : IN std_logic;   
              avm_m1_address          : OUT std_logic_vector(31 DOWNTO 0);   
              avm_m1_byteenable       : OUT std_logic_vector(3 DOWNTO 0);   
              avm_m1_read_n           : OUT std_logic;   
              avm_m1_readdata         : IN std_logic_vector(31 DOWNTO 0);   
              avm_m1_waitrequest      : IN std_logic;   
              addr_reg                : IN std_logic_vector(31 DOWNTO 0);   
              len_reg                 : IN std_logic_vector(15 DOWNTO 0);   
              go                      : IN std_logic;   
              avm_m1_byteenable_mask  : OUT std_logic_vector(3 DOWNTO 0);   
              read_busy               : OUT std_logic;   
              data_in_ready           : OUT std_logic;   
              count                   : OUT std_logic_vector(15 DOWNTO 0);   
              data_to_process         : OUT std_logic_vector(31 DOWNTO 0));   
END ENTITY read_master;

ARCHITECTURE translated OF read_master IS


       SIGNAL avm_m1_address_xhdl1     :  std_logic_vector(31 DOWNTO 0);   
       -- Check for valid read data on the master port by looking for waitrequest with each read
       --wire [31:0] address = addr;
       SIGNAL temp_xhdl9               :  std_logic;   
       SIGNAL data_in_ready_xhdl6      :  std_logic;   
       -- mask data to process based on byteenable mask
       -- passing readdata to task logic
       SIGNAL temp_xhdl10              :  std_logic_vector(31 DOWNTO 0);   
       SIGNAL temp_xhdl11              :  std_logic_vector(31 DOWNTO 0);   
       SIGNAL temp_xhdl12              :  std_logic_vector(31 DOWNTO 0);   
       SIGNAL addr                     :  std_logic_vector(31 DOWNTO 0);   
       SIGNAL count_tmp                :  std_logic_vector(15 DOWNTO 0);   
       SIGNAL avm_m1_byteenable_xhdl2  :  std_logic_vector(3 DOWNTO 0);   
       SIGNAL avm_m1_read_n_xhdl3      :  std_logic;   
       SIGNAL avm_m1_byteenable_mask_xhdl4    :  std_logic_vector(3 DOWNTO 0);   
       SIGNAL read_busy_xhdl5          :  std_logic;   
       SIGNAL count_xhdl7              :  std_logic_vector(15 DOWNTO 0);   
       SIGNAL data_to_process_xhdl8    :  std_logic_vector(31 DOWNTO 0);   

BEGIN
       avm_m1_address <= avm_m1_address_xhdl1;
       avm_m1_byteenable <= avm_m1_byteenable_xhdl2;
       avm_m1_read_n <= avm_m1_read_n_xhdl3;
       avm_m1_byteenable_mask <= avm_m1_byteenable_mask_xhdl4;
       read_busy <= read_busy_xhdl5;
       data_in_ready <= data_in_ready_xhdl6;
       count <= count_xhdl7;
       data_to_process <= data_to_process_xhdl8;
       avm_m1_address_xhdl1 <= addr(31 DOWNTO 2) & "00" ;
       temp_xhdl9 <= '1' WHEN ((avm_m1_read_n_xhdl3 = '0') AND  avm_m1_waitrequest = '0') ELSE '0';
       data_in_ready_xhdl6 <= temp_xhdl9 ;
       
       --temp_xhdl10 <= ("00000000111111111111111111111111" AND avm_m1_readdata(31 DOWNTO 0)) WHEN (avm_m1_byteenable_mask_xhdl4 = "0111") ELSE avm_m1_readdata(31 DOWNTO 0);
       --temp_xhdl11 <= ("00000000000000001111111111111111" AND avm_m1_readdata(31 DOWNTO 0)) WHEN (avm_m1_byteenable_mask_xhdl4 = "0011") ELSE temp_xhdl10;
       --temp_xhdl12 <= ("00000000000000000000000011111111" AND avm_m1_readdata(31 DOWNTO 0)) WHEN (avm_m1_byteenable_mask_xhdl4 = "0001") ELSE temp_xhdl11;
       --data_to_process_xhdl8(31 DOWNTO 0) <= temp_xhdl12 ;
       data_to_process_xhdl8(31 downto 0) <=
        ("00000000111111111111111111111111" AND avm_m1_readdata(31 DOWNTO 0)) WHEN (avm_m1_byteenable_mask_xhdl4 = "0111") ELSE
        ("00000000000000001111111111111111" AND avm_m1_readdata(31 DOWNTO 0)) WHEN (avm_m1_byteenable_mask_xhdl4 = "0011") ELSE
        ("00000000000000000000000011111111" AND avm_m1_readdata(31 DOWNTO 0)) WHEN (avm_m1_byteenable_mask_xhdl4 = "0001") ELSE
        avm_m1_readdata(31 DOWNTO 0);
       
       -------
       avm_m1_byteenable_xhdl2 <= "1111" ;

       PROCESS
       BEGIN
              WAIT UNTIL (gls_clk'EVENT AND gls_clk = '1') OR (gls_reset_n'EVENT AND gls_reset_n = '0');
              IF (gls_reset_n = '0') THEN
                     count_tmp <= "0000000000000000";    
                     read_busy_xhdl5 <= '0';    
                     addr <= "00000000000000000000000000000000";    
                     avm_m1_byteenable_mask_xhdl4 <= "0000";    
                     avm_m1_read_n_xhdl3 <= '1';    
                     read_busy_xhdl5 <= '0';    
              ELSE
                    IF (go = '1') THEN
                            count_tmp <= len_reg - "0000000000000100";    
                            addr <= addr_reg;    
                            avm_m1_byteenable_mask_xhdl4 <= "1111";    
                            avm_m1_read_n_xhdl3 <= '1';    
                            read_busy_xhdl5 <= '1';    
                    ELSIF ((count_xhdl7 > "0000000000000011") AND data_in_ready_xhdl6 = '1') THEN
                                   count_tmp <= count_tmp - "0000000000000100";    
                                   addr <= addr + "00000000000000000000000000000100";    
                                   avm_m1_byteenable_mask_xhdl4 <= "1111";    
                                   avm_m1_read_n_xhdl3 <= '0';    
                                   read_busy_xhdl5 <= '1';    
                    ELSIF ((count_xhdl7 = "0000000000000011") AND data_in_ready_xhdl6 = '1') THEN
                                          count_tmp <= count_tmp - "0000000000000011";    
                                          addr <= addr + "00000000000000000000000000000100";    
                                          avm_m1_byteenable_mask_xhdl4 <= "0111";    
                                          avm_m1_read_n_xhdl3 <= '0';    
                                          read_busy_xhdl5 <= '1';    
                    ELSIF ((count_xhdl7 = "0000000000000010") AND data_in_ready_xhdl6 = '1') THEN
                                                 count_tmp <= count_tmp - "0000000000000010";    
                                                 addr <= addr + "00000000000000000000000000000100";    
                                                 avm_m1_byteenable_mask_xhdl4 <= "0011";    
                                                 avm_m1_read_n_xhdl3 <= '0';    
                                                 read_busy_xhdl5 <= '1';    
                    ELSIF ((count_xhdl7 = "0000000000000001") AND data_in_ready_xhdl6 = '1') THEN
                                                        count_tmp <= count_tmp - "0000000000000001";    
                                                        addr <= addr + "00000000000000000000000000000100";    
                                                        avm_m1_byteenable_mask_xhdl4 <= "0001";    
                                                        avm_m1_read_n_xhdl3 <= '0';    
                                                        read_busy_xhdl5 <= '1';    
                    ELSIF ((count_xhdl7 = "0000000000000000") AND NOT data_in_ready_xhdl6 = '1') THEN
                                                               count_tmp <= count_tmp;    
                                                               addr <= addr;    
                                                               avm_m1_byteenable_mask_xhdl4 <= avm_m1_byteenable_mask_xhdl4;    
                                                               avm_m1_read_n_xhdl3 <= avm_m1_read_n_xhdl3;    
                                                               read_busy_xhdl5 <= read_busy_xhdl5;    
                    ELSIF (count_xhdl7 = "0000000000000000") THEN
                                                                      addr <= "00000000000000000000000000000000";    
                                                                      avm_m1_byteenable_mask_xhdl4 <= "0000";    
                                                                      avm_m1_read_n_xhdl3 <= '1';    
                                                                      read_busy_xhdl5 <= '0';    
                    ELSE
                     		count_tmp <= count_tmp;    
                        addr <= addr;    
                        avm_m1_byteenable_mask_xhdl4 <= avm_m1_byteenable_mask_xhdl4;    
                        avm_m1_read_n_xhdl3 <= '0';    
                        read_busy_xhdl5 <= '1';    
                    END IF;                                                        
              END IF;
       END PROCESS;
       count_xhdl7 <= count_tmp ;

END ARCHITECTURE translated;