📄 s1_slave.vhd
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--
-- VHDL file generated by X-HDL - Revision 3.2.37 Dec. 3, 2003
-- Thu Jun 19 11:30:21 2008
--
-- Input file : E:/DE2_WEB/altera_avalon_checksum/hdl/s1_slave.v
-- Design name : s1_slave
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--*****************************************************************************
-- *****************************************************************************
-- * *
-- * License Agreement *
-- * *
-- * Copyright (c) 2007 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Permission is hereby granted, free of charge, to any person obtaining a *
-- * copy of this software and associated documentation files (the "Software"), *
-- * to deal in the Software without restriction, including without limitation *
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense, *
-- * and/or sell copies of the Software, and to permit persons to whom the *
-- * Software is furnished to do so, subject to the following conditions: *
-- * *
-- * The above copyright notice and this permission notice shall be included in *
-- * all copies or substantial portions of the Software. *
-- * *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
-- * DEALINGS IN THE SOFTWARE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- *****************************************************************************
ENTITY s1_slave IS
PORT (
gls_clk : IN bit;
gls_reset_n : IN bit;
avs_s1_address : IN bit_vector(2 DOWNTO 0);
avs_s1_read_n : IN bit;
avs_s1_write_n : IN bit;
avs_s1_writedata : IN bit_vector(31 DOWNTO 0);
avs_s1_readdata : OUT bit_vector(31 DOWNTO 0);
avs_s1_chipselect_n : IN bit;
addr_reg : OUT bit_vector(31 DOWNTO 0);
len_reg : OUT bit_vector(15 DOWNTO 0);
go : OUT bit;
read_busy : IN bit;
edge_pulse : OUT bit;
result : IN bit_vector(15 DOWNTO 0));
END s1_slave;
ARCHITECTURE translated OF s1_slave IS
-- Module contents
SIGNAL result_32 : bit_vector(31 DOWNTO 0);
SIGNAL status_32 : bit_vector(31 DOWNTO 0);
SIGNAL cntl_reg : bit_vector(2 DOWNTO 0);
SIGNAL read_done : bit;
SIGNAL edge_detect_reg : bit;
SIGNAL read_data_reg : bit_vector(31 DOWNTO 0);
--define the write register offsets
CONSTANT ADDR : bit_vector(2 DOWNTO 0) := "000";
CONSTANT LEN : bit_vector(2 DOWNTO 0) := "001";
CONSTANT CNTL : bit_vector(2 DOWNTO 0) := "010";
CONSTANT RESERVED1 : bit_vector(2 DOWNTO 0) := "011";
--Define the read register offsets
CONSTANT RESULT_xhdl6 : bit_vector(2 DOWNTO 0) := "100";
CONSTANT STATUS : bit_vector(2 DOWNTO 0) := "101";
CONSTANT RESERVED2 : bit_vector(2 DOWNTO 0) := "110";
CONSTANT RESERVED3 : bit_vector(2 DOWNTO 0) := "111";
SIGNAL temp_xhdl7 : bit_vector(31 DOWNTO 0);
SIGNAL temp_xhdl8 : bit_vector(31 DOWNTO 0);
SIGNAL temp_xhdl9 : bit_vector(31 DOWNTO 0);
SIGNAL temp_xhdl10 : bit_vector(31 DOWNTO 0);
SIGNAL avs_s1_readdata_xhdl1 : bit_vector(31 DOWNTO 0);
SIGNAL addr_reg_xhdl2 : bit_vector(31 DOWNTO 0);
SIGNAL len_reg_xhdl3 : bit_vector(15 DOWNTO 0);
SIGNAL go_xhdl4 : bit;
SIGNAL edge_pulse_xhdl5 : bit;
BEGIN
--avs_s1_readdata <= avs_s1_readdata_xhdl1;
avs_s1_readdata <= x"c1d3_2a5f";
addr_reg <= addr_reg_xhdl2;
len_reg <= len_reg_xhdl3;
go <= go_xhdl4;
edge_pulse <= edge_pulse_xhdl5;
go_xhdl4 <= cntl_reg(0) ;
PROCESS
BEGIN
WAIT UNTIL (gls_clk'EVENT AND gls_clk = '1') OR (gls_reset_n'EVENT AND gls_reset_n = '0');
IF (gls_reset_n = '0') THEN
addr_reg_xhdl2 <= "00000000000000000000000000000000";
len_reg_xhdl3 <= "0000000000000000";
cntl_reg <= "000";
ELSE
IF (avs_s1_chipselect_n = '0' AND avs_s1_write_n = '0') THEN
CASE avs_s1_address(2 DOWNTO 0) IS
WHEN ADDR =>
IF (NOT read_busy = '1') THEN
addr_reg_xhdl2 <= avs_s1_writedata(31 DOWNTO 0);
ELSE
addr_reg_xhdl2 <= addr_reg_xhdl2;
END IF;
WHEN LEN =>
IF (NOT read_busy = '1') THEN
len_reg_xhdl3 <= avs_s1_writedata(15 DOWNTO 0);
ELSE
len_reg_xhdl3 <= len_reg_xhdl3;
END IF;
WHEN CNTL =>
IF (NOT read_busy = '1') THEN
cntl_reg <= avs_s1_writedata(2 DOWNTO 0);
ELSE
cntl_reg <= cntl_reg;
END IF;
WHEN OTHERS =>
addr_reg_xhdl2 <= addr_reg_xhdl2;
len_reg_xhdl3 <= len_reg_xhdl3;
cntl_reg <= cntl_reg;
END CASE;
END IF;
IF (go_xhdl4 = '1') THEN
cntl_reg(0) <= '0';
END IF;
END IF;
END PROCESS;
--temp_xhdl7 <= "000000000000000000000000000000" & read_done & read_busy WHEN (avs_s1_address = STATUS) ELSE addr_reg_xhdl2;
--temp_xhdl8 <= "0000000000000000" & result(15 DOWNTO 0) WHEN (avs_s1_address = RESULT_xhdl6) ELSE temp_xhdl7;
--temp_xhdl9 <= "00000000000000000000000000000" & cntl_reg(2 DOWNTO 0) WHEN (avs_s1_address = CNTL) ELSE temp_xhdl8;
--temp_xhdl10 <= "0000000000000000" & len_reg_xhdl3(15 DOWNTO 0) WHEN (avs_s1_address = LEN) ELSE temp_xhdl9;
temp_xhdl10 <=
"000000000000000000000000001010" & '1' & '1' WHEN (avs_s1_address = STATUS) ELSE
"0000000000000000" & result(15 DOWNTO 0) WHEN (avs_s1_address = RESULT_xhdl6) ELSE
"00000000000000000000000000000" & cntl_reg(2 DOWNTO 0) WHEN (avs_s1_address = CNTL) ELSE
"0000000000000000" & len_reg_xhdl3(15 DOWNTO 0) WHEN (avs_s1_address = LEN) ELSE
addr_reg_xhdl2;
PROCESS
BEGIN
WAIT UNTIL (gls_clk'EVENT AND gls_clk = '1') OR (gls_reset_n'EVENT AND gls_reset_n = '0');
IF (gls_reset_n = '0') THEN
read_data_reg <= "00000000000000000000000000000000";
ELSE
read_data_reg <= temp_xhdl10;
END IF;
END PROCESS;
avs_s1_readdata_xhdl1 <= read_data_reg ;
PROCESS
BEGIN
WAIT UNTIL (gls_clk'EVENT AND gls_clk = '1') OR (gls_reset_n'EVENT AND gls_reset_n = '0');
IF (gls_reset_n = '0') THEN
edge_detect_reg <= '0';
ELSE
IF (gls_clk = '1') THEN
edge_detect_reg <= read_busy;
END IF;
END IF;
END PROCESS;
edge_pulse_xhdl5 <= NOT (read_busy OR NOT edge_detect_reg) ;
PROCESS
BEGIN
WAIT UNTIL (gls_clk'EVENT AND gls_clk = '1') OR (gls_reset_n'EVENT AND gls_reset_n = '0');
IF (gls_reset_n = '0') THEN
read_done <= '0';
ELSE
IF (edge_pulse_xhdl5 = '1') THEN
read_done <= '1';
ELSE
IF (go_xhdl4 = '1') THEN
read_done <= '0';
ELSE
read_done <= read_done;
END IF;
END IF;
END IF;
END PROCESS;
END translated;
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