📄 class.ptf
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FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "E:/DE2_WEB/altera_avalon_chk_vhd/hdl/altera_avalon_checksum.vhd";
}
}
top_module_name = "altera_avalon_checksum";
emit_system_h = "0";
LIBRARIES
{
library = "ieee.std_logic_1164.all";
library = "ieee.std_logic_arith.all";
library = "ieee.std_logic_unsigned.all";
library = "std.standard.all";
}
}
MODULE_DEFAULTS global_signals
{
class = "altera_avalon_checksum";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT avs_s1_address
{
width = "3";
width_expression = "";
direction = "input";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avs_s1_chipselect_n
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avs_s1_read_n
{
width = "1";
width_expression = "";
direction = "input";
type = "read_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avs_s1_write_n
{
width = "1";
width_expression = "";
direction = "input";
type = "write_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avs_s1_writedata
{
width = "32";
width_expression = "";
direction = "input";
type = "writedata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avs_s1_readdata
{
width = "32";
width_expression = "";
direction = "output";
type = "readdata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
MASTER m1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT avm_m1_address
{
width = "32";
width_expression = "";
direction = "output";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avm_m1_byteenable
{
width = "4";
width_expression = "";
direction = "output";
type = "byteenable";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avm_m1_read_n
{
width = "1";
width_expression = "";
direction = "output";
type = "read_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avm_m1_readdata
{
width = "32";
width_expression = "";
direction = "input";
type = "readdata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avm_m1_waitrequest
{
width = "1";
width_expression = "";
direction = "input";
type = "waitrequest";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
PORT_WIRING
{
PORT gls_clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT gls_reset_n
{
width = "1";
width_expression = "";
direction = "input";
type = "reset_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "altera_avalon_checksum";
technology = "imported components";
}
}
SOPC_Builder_Version = "0.0";
}
}
}
FILE checksum_task_logic.vhd
{
file_mod = "Sat Jun 21 17:53:21 CST 2008";
quartus_map_start = "Sat Jun 21 17:55:55 CST 2008";
quartus_map_finished = "Sat Jun 21 17:55:59 CST 2008";
#found 1 valid modules
WRAPPER checksum_task_logic
{
CLASS checksum_task_logic
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "E:/DE2_WEB/altera_avalon_chk_vhd/hdl/checksum_task_logic.vhd";
}
}
top_module_name = "checksum_task_logic";
emit_system_h = "0";
LIBRARIES
{
library = "ieee.std_logic_1164.all";
library = "ieee.std_logic_arith.all";
library = "ieee.std_logic_unsigned.all";
library = "std.standard.all";
}
}
MODULE_DEFAULTS global_signals
{
class = "checksum_task_logic";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT data_to_process
{
width = "32";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT go
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT data_in_ready
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT result
{
width = "16";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
PORT_WIRING
{
PORT gls_clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT gls_reset_n
{
width = "1";
width_expression = "";
direction = "input";
type = "reset_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "checksum_task_logic";
technology = "imported components";
}
}
SOPC_Builder_Version = "0.0";
}
}
}
FILE read_master.vhd
{
file_mod = "Thu Jun 19 18:02:28 CST 2008";
quartus_map_start = "Sat Jun 21 17:55:59 CST 2008";
quartus_map_finished = "Sat Jun 21 17:56:02 CST 2008";
#found 1 valid modules
WRAPPER read_master
{
CLASS read_master
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "E:/DE2_WEB/altera_avalon_chk_vhd/hdl/read_master.vhd";
}
}
top_module_name = "read_master";
emit_system_h = "0";
LIBRARIES
{
library = "ieee.std_logic_1164.all";
library = "ieee.std_logic_arith.all";
library = "ieee.std_logic_unsigned.all";
library = "std.standard.all";
}
}
MODULE_DEFAULTS global_signals
{
class = "read_master";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
MASTER m1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT avm_m1_address
{
width = "32";
width_expression = "";
direction = "output";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avm_m1_byteenable
{
width = "4";
width_expression = "";
direction = "output";
type = "byteenable";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avm_m1_read_n
{
width = "1";
width_expression = "";
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