class.ptf

de2 avalon checksum by vhdl

#
# This class.ptf file built by Component Editor
# 2008.06.21.23:23:48
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS altera_avalon_chk_vhd
{
   CB_GENERATOR 
   {
      HDL_FILES 
      {
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "vhdl";
            filepath = "hdl/altera_avalon_checksum.vhd";
         }
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "vhdl";
            filepath = "hdl/checksum_task_logic.vhd";
         }
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "vhdl";
            filepath = "hdl/read_master.vhd";
         }
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "vhdl";
            filepath = "hdl/s1_slave.vhd";
         }
      }
      top_module_name = "altera_avalon_checksum.vhd:altera_avalon_checksum";
      emit_system_h = "1";
      LIBRARIES 
      {
         library = "ieee.std_logic_1164.all";
         library = "ieee.std_logic_arith.all";
         library = "ieee.std_logic_unsigned.all";
         library = "std.standard.all";
      }
   }
   MODULE_DEFAULTS global_signals
   {
      class = "altera_avalon_chk_vhd";
      class_version = "1.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Has_Clock = "1";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      PORT_WIRING 
      {
         PORT gls_clk
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "clk";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT gls_reset_n
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         hdl_parameters 
         {
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "1";
            Has_Clock = "0";
            Address_Width = "3";
            Address_Alignment = "native";
            Data_Width = "32";
            Has_Base_Address = "1";
            Has_IRQ = "0";
            Setup_Time = "0cycles";
            Hold_Time = "0cycles";
            Read_Wait_States = "1cycles";
            Write_Wait_States = "0cycles";
            Read_Latency = "0";
            Maximum_Pending_Read_Transactions = "0";
            Active_CS_Through_Read_Latency = "0";
            Is_Printable_Device = "0";
            Is_Memory_Device = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            Minimum_Uninterrupted_Run_Length = "1";
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "0";
               Read_Wait_Value = "1";
               Write_Wait_Value = "0";
               Hold_Value = "0";
               Timing_Units = "cycles";
               Read_Latency_Value = "0";
               Minimum_Arbitration_Shares = "1";
               Active_CS_Through_Read_Latency = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "native";
               Is_Printable_Device = "0";
               Interleave_Bursts = "0";
               interface_name = "Avalon Slave";
               external_wait = "0";
               Is_Memory_Device = "0";
            }
         }
         PORT_WIRING 
         {
            PORT avs_s1_address
            {
               width = "3";
               width_expression = "";
               direction = "input";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avs_s1_chipselect_n
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "chipselect_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avs_s1_read_n
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "read_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avs_s1_write_n
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "write_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avs_s1_writedata
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avs_s1_readdata
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
      MASTER m1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "2";
            Has_Clock = "0";
            Address_Width = "32";
            Data_Width = "32";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Is_Asynchronous = "0";
            Has_IRQ = "0";
            Irq_Scheme = "none";
            Interrupt_Range = "";
            Is_Readable = "1";
            Is_Writable = "0";
            Is_Big_Endian = "0";
            Register_Outgoing_Signals = "0";
         }
         COMPONENT_BUILDER 
         {
            AVM_SETTINGS 
            {
               stream_reads = "0";
               stream_writes = "0";
               irq_width = "0";
               irq_number_width = "0";
               irq_scheme = "none";
               Is_Asynchronous = "0";
               Is_Big_Endian = "0";
            }
         }
         PORT_WIRING 
         {
            PORT avm_m1_address
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avm_m1_byteenable
            {
               width = "4";
               width_expression = "";
               direction = "output";
               type = "byteenable";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avm_m1_read_n
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "read_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avm_m1_readdata
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avm_m1_waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "altera_avalon_chk_vhd";
         technology = "Shane";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "altera_avalon_chk_vhd - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_s1 = "SLAVE s1/SYSTEM_BUILDER_INFO";
            SBI_m1 = "MASTER m1/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>altera_avalon_chk_vhd 1.0</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2008.06.21.23:23:48";
               }
               TEXT 
               {
                  title = "Class name: altera_avalon_chk_vhd";
               }
               TEXT 
               {
                  title = "Class version: 1.0";
               }
               TEXT 
               {
                  title = "Component name: altera_avalon_chk_vhd";
               }
               TEXT 
               {
                  title = "Component Group: Shane";
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "6.00";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
      }
      SW_FILES 
      {
         FILE 
         {
            filepath = "inc/altera_avalon_chk_vhd_regs.h";
            type = "Registers (inc/)";
         }
      }
      built_on = "2008.06.21.23:23:48";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE altera_avalon_checksum.vhd
         {
            file_mod = "Sat Jun 21 17:33:52 CST 2008";
            quartus_map_start = "Sat Jun 21 17:55:51 CST 2008";
            quartus_map_finished = "Sat Jun 21 17:55:55 CST 2008";
            #found 1 valid modules
            WRAPPER altera_avalon_checksum
            {
               CLASS altera_avalon_checksum
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {