prev_cmp_jian.tan.qmsg

1、 掌握VHDL的结构以及实例的编程； 2、 学会使用QuartusⅡ平台的开化； 3、 设计一个2位BCD码加法器。

{ "Info" "ITDB_TH_RESULT" "y6\[0\]\$latch A1\[2\] key -3.244 ns register " "Info: th for register \"y6\[0\]\$latch\" (data pin = \"A1\[2\]\", clock pin = \"key\") is -3.244 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key destination 2.625 ns + Longest register " "Info: + Longest clock path from clock \"key\" to destination register is 2.625 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns key 1 CLK PIN_W26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 1; CLK Node = 'key'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.091 ns) + CELL(0.155 ns) 1.108 ns key~clk_delay_ctrl 2 COMB CLKDELAYCTRL_G7 1 " "Info: 2: + IC(0.091 ns) + CELL(0.155 ns) = 1.108 ns; Loc. = CLKDELAYCTRL_G7; Fanout = 1; COMB Node = 'key~clk_delay_ctrl'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.246 ns" { key key~clk_delay_ctrl } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.108 ns key~clkctrl 3 COMB CLKCTRL_G7 15 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 1.108 ns; Loc. = CLKCTRL_G7; Fanout = 15; COMB Node = 'key~clkctrl'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { key~clk_delay_ctrl key~clkctrl } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.150 ns) 2.625 ns y6\[0\]\$latch 4 REG LCCOMB_X32_Y8_N6 4 " "Info: 4: + IC(1.367 ns) + CELL(0.150 ns) = 2.625 ns; Loc. = LCCOMB_X32_Y8_N6; Fanout = 4; REG Node = 'y6\[0\]\$latch'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.517 ns" { key~clkctrl y6[0]$latch } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.167 ns ( 44.46 % ) " "Info: Total cell delay = 1.167 ns ( 44.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.458 ns ( 55.54 % ) " "Info: Total interconnect delay = 1.458 ns ( 55.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { key key~clk_delay_ctrl key~clkctrl y6[0]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { key {} key~combout {} key~clk_delay_ctrl {} key~clkctrl {} y6[0]$latch {} } { 0.000ns 0.000ns 0.091ns 0.000ns 1.367ns } { 0.000ns 0.862ns 0.155ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.869 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns A1\[2\] 1 PIN PIN_AC13 9 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AC13; Fanout = 9; PIN Node = 'A1\[2\]'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1[2] } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.842 ns) + CELL(0.416 ns) 3.247 ns Add2~35 2 COMB LCCOMB_X64_Y8_N10 3 " "Info: 2: + IC(1.842 ns) + CELL(0.416 ns) = 3.247 ns; Loc. = LCCOMB_X64_Y8_N10; Fanout = 3; COMB Node = 'Add2~35'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.258 ns" { A1[2] Add2~35 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.660 ns) + CELL(0.271 ns) 5.178 ns LessThan1~33 3 COMB LCCOMB_X32_Y8_N30 5 " "Info: 3: + IC(1.660 ns) + CELL(0.271 ns) = 5.178 ns; Loc. = LCCOMB_X32_Y8_N30; Fanout = 5; COMB Node = 'LessThan1~33'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.931 ns" { Add2~35 LessThan1~33 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.420 ns) 5.869 ns y6\[0\]\$latch 4 REG LCCOMB_X32_Y8_N6 4 " "Info: 4: + IC(0.271 ns) + CELL(0.420 ns) = 5.869 ns; Loc. = LCCOMB_X32_Y8_N6; Fanout = 4; REG Node = 'y6\[0\]\$latch'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.691 ns" { LessThan1~33 y6[0]$latch } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.096 ns ( 35.71 % ) " "Info: Total cell delay = 2.096 ns ( 35.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.773 ns ( 64.29 % ) " "Info: Total interconnect delay = 3.773 ns ( 64.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.869 ns" { A1[2] Add2~35 LessThan1~33 y6[0]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "5.869 ns" { A1[2] {} A1[2]~combout {} Add2~35 {} LessThan1~33 {} y6[0]$latch {} } { 0.000ns 0.000ns 1.842ns 1.660ns 0.271ns } { 0.000ns 0.989ns 0.416ns 0.271ns 0.420ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { key key~clk_delay_ctrl key~clkctrl y6[0]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { key {} key~combout {} key~clk_delay_ctrl {} key~clkctrl {} y6[0]$latch {} } { 0.000ns 0.000ns 0.091ns 0.000ns 1.367ns } { 0.000ns 0.862ns 0.155ns 0.000ns 0.150ns } "" } } { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.869 ns" { A1[2] Add2~35 LessThan1~33 y6[0]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "5.869 ns" { A1[2] {} A1[2]~combout {} Add2~35 {} LessThan1~33 {} y6[0]$latch {} } { 0.000ns 0.000ns 1.842ns 1.660ns 0.271ns } { 0.000ns 0.989ns 0.416ns 0.271ns 0.420ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 17 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Allocated 125 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 19 02:30:26 2008 " "Info: Processing ended: Thu Jun 19 02:30:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}