prev_cmp_jian.tan.qmsg

1、 掌握VHDL的结构以及实例的编程； 2、 学会使用QuartusⅡ平台的开化； 3、 设计一个2位BCD码加法器。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "key " "Info: Assuming node \"key\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "y5\[4\]\$latch B1\[1\] key 13.243 ns register " "Info: tsu for register \"y5\[4\]\$latch\" (data pin = \"B1\[1\]\", clock pin = \"key\") is 13.243 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.151 ns + Longest pin register " "Info: + Longest pin to register delay is 15.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns B1\[1\] 1 PIN PIN_T7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_T7; Fanout = 9; PIN Node = 'B1\[1\]'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1[1] } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.177 ns) + CELL(0.393 ns) 7.402 ns Add2~34 2 COMB LCCOMB_X64_Y8_N8 2 " "Info: 2: + IC(6.177 ns) + CELL(0.393 ns) = 7.402 ns; Loc. = LCCOMB_X64_Y8_N8; Fanout = 2; COMB Node = 'Add2~34'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.570 ns" { B1[1] Add2~34 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.473 ns Add2~36 3 COMB LCCOMB_X64_Y8_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 7.473 ns; Loc. = LCCOMB_X64_Y8_N10; Fanout = 2; COMB Node = 'Add2~36'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~34 Add2~36 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.544 ns Add2~38 4 COMB LCCOMB_X64_Y8_N12 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 7.544 ns; Loc. = LCCOMB_X64_Y8_N12; Fanout = 1; COMB Node = 'Add2~38'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~36 Add2~38 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 7.954 ns Add2~39 5 COMB LCCOMB_X64_Y8_N14 1 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 7.954 ns; Loc. = LCCOMB_X64_Y8_N14; Fanout = 1; COMB Node = 'Add2~39'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add2~38 Add2~39 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.171 ns) + CELL(0.420 ns) 10.545 ns LessThan1~33 6 COMB LCCOMB_X32_Y8_N30 5 " "Info: 6: + IC(2.171 ns) + CELL(0.420 ns) = 10.545 ns; Loc. = LCCOMB_X32_Y8_N30; Fanout = 5; COMB Node = 'LessThan1~33'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { Add2~39 LessThan1~33 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.393 ns) 11.209 ns Add4~11 7 COMB LCCOMB_X32_Y8_N8 2 " "Info: 7: + IC(0.271 ns) + CELL(0.393 ns) = 11.209 ns; Loc. = LCCOMB_X32_Y8_N8; Fanout = 2; COMB Node = 'Add4~11'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.664 ns" { LessThan1~33 Add4~11 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 11.619 ns Add4~12 8 COMB LCCOMB_X32_Y8_N10 8 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 11.619 ns; Loc. = LCCOMB_X32_Y8_N10; Fanout = 8; COMB Node = 'Add4~12'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add4~11 Add4~12 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.438 ns) 12.402 ns Mux37~3 9 COMB LCCOMB_X32_Y8_N26 1 " "Info: 9: + IC(0.345 ns) + CELL(0.438 ns) = 12.402 ns; Loc. = LCCOMB_X32_Y8_N26; Fanout = 1; COMB Node = 'Mux37~3'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { Add4~12 Mux37~3 } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.329 ns) + CELL(0.420 ns) 15.151 ns y5\[4\]\$latch 10 REG LCCOMB_X2_Y12_N8 1 " "Info: 10: + IC(2.329 ns) + CELL(0.420 ns) = 15.151 ns; Loc. = LCCOMB_X2_Y12_N8; Fanout = 1; REG Node = 'y5\[4\]\$latch'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.749 ns" { Mux37~3 y5[4]$latch } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.858 ns ( 25.46 % ) " "Info: Total cell delay = 3.858 ns ( 25.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.293 ns ( 74.54 % ) " "Info: Total interconnect delay = 11.293 ns ( 74.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.151 ns" { B1[1] Add2~34 Add2~36 Add2~38 Add2~39 LessThan1~33 Add4~11 Add4~12 Mux37~3 y5[4]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "15.151 ns" { B1[1] {} B1[1]~combout {} Add2~34 {} Add2~36 {} Add2~38 {} Add2~39 {} LessThan1~33 {} Add4~11 {} Add4~12 {} Mux37~3 {} y5[4]$latch {} } { 0.000ns 0.000ns 6.177ns 0.000ns 0.000ns 0.000ns 2.171ns 0.271ns 0.000ns 0.345ns 2.329ns } { 0.000ns 0.832ns 0.393ns 0.071ns 0.071ns 0.410ns 0.420ns 0.393ns 0.410ns 0.438ns 0.420ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.672 ns + " "Info: + Micro setup delay of destination is 0.672 ns" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key destination 2.580 ns - Shortest register " "Info: - Shortest clock path from clock \"key\" to destination register is 2.580 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns key 1 CLK PIN_W26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 1; CLK Node = 'key'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.091 ns) + CELL(0.155 ns) 1.108 ns key~clk_delay_ctrl 2 COMB CLKDELAYCTRL_G7 1 " "Info: 2: + IC(0.091 ns) + CELL(0.155 ns) = 1.108 ns; Loc. = CLKDELAYCTRL_G7; Fanout = 1; COMB Node = 'key~clk_delay_ctrl'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.246 ns" { key key~clk_delay_ctrl } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.108 ns key~clkctrl 3 COMB CLKCTRL_G7 15 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 1.108 ns; Loc. = CLKCTRL_G7; Fanout = 15; COMB Node = 'key~clkctrl'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { key~clk_delay_ctrl key~clkctrl } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.150 ns) 2.580 ns y5\[4\]\$latch 4 REG LCCOMB_X2_Y12_N8 1 " "Info: 4: + IC(1.322 ns) + CELL(0.150 ns) = 2.580 ns; Loc. = LCCOMB_X2_Y12_N8; Fanout = 1; REG Node = 'y5\[4\]\$latch'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.472 ns" { key~clkctrl y5[4]$latch } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.167 ns ( 45.23 % ) " "Info: Total cell delay = 1.167 ns ( 45.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.413 ns ( 54.77 % ) " "Info: Total interconnect delay = 1.413 ns ( 54.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.580 ns" { key key~clk_delay_ctrl key~clkctrl y5[4]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.580 ns" { key {} key~combout {} key~clk_delay_ctrl {} key~clkctrl {} y5[4]$latch {} } { 0.000ns 0.000ns 0.091ns 0.000ns 1.322ns } { 0.000ns 0.862ns 0.155ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.151 ns" { B1[1] Add2~34 Add2~36 Add2~38 Add2~39 LessThan1~33 Add4~11 Add4~12 Mux37~3 y5[4]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "15.151 ns" { B1[1] {} B1[1]~combout {} Add2~34 {} Add2~36 {} Add2~38 {} Add2~39 {} LessThan1~33 {} Add4~11 {} Add4~12 {} Mux37~3 {} y5[4]$latch {} } { 0.000ns 0.000ns 6.177ns 0.000ns 0.000ns 0.000ns 2.171ns 0.271ns 0.000ns 0.345ns 2.329ns } { 0.000ns 0.832ns 0.393ns 0.071ns 0.071ns 0.410ns 0.420ns 0.393ns 0.410ns 0.438ns 0.420ns } "" } } { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.580 ns" { key key~clk_delay_ctrl key~clkctrl y5[4]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.580 ns" { key {} key~combout {} key~clk_delay_ctrl {} key~clkctrl {} y5[4]$latch {} } { 0.000ns 0.000ns 0.091ns 0.000ns 1.322ns } { 0.000ns 0.862ns 0.155ns 0.000ns 0.150ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "key y5\[0\] y5\[0\]\$latch 8.622 ns register " "Info: tco from clock \"key\" to destination pin \"y5\[0\]\" through register \"y5\[0\]\$latch\" is 8.622 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key source 2.625 ns + Longest register " "Info: + Longest clock path from clock \"key\" to source register is 2.625 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns key 1 CLK PIN_W26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 1; CLK Node = 'key'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.091 ns) + CELL(0.155 ns) 1.108 ns key~clk_delay_ctrl 2 COMB CLKDELAYCTRL_G7 1 " "Info: 2: + IC(0.091 ns) + CELL(0.155 ns) = 1.108 ns; Loc. = CLKDELAYCTRL_G7; Fanout = 1; COMB Node = 'key~clk_delay_ctrl'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.246 ns" { key key~clk_delay_ctrl } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.108 ns key~clkctrl 3 COMB CLKCTRL_G7 15 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 1.108 ns; Loc. = CLKCTRL_G7; Fanout = 15; COMB Node = 'key~clkctrl'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { key~clk_delay_ctrl key~clkctrl } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.150 ns) 2.625 ns y5\[0\]\$latch 4 REG LCCOMB_X32_Y8_N16 1 " "Info: 4: + IC(1.367 ns) + CELL(0.150 ns) = 2.625 ns; Loc. = LCCOMB_X32_Y8_N16; Fanout = 1; REG Node = 'y5\[0\]\$latch'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.517 ns" { key~clkctrl y5[0]$latch } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.167 ns ( 44.46 % ) " "Info: Total cell delay = 1.167 ns ( 44.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.458 ns ( 55.54 % ) " "Info: Total interconnect delay = 1.458 ns ( 55.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { key key~clk_delay_ctrl key~clkctrl y5[0]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { key {} key~combout {} key~clk_delay_ctrl {} key~clkctrl {} y5[0]$latch {} } { 0.000ns 0.000ns 0.091ns 0.000ns 1.367ns } { 0.000ns 0.862ns 0.155ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.997 ns + Longest register pin " "Info: + Longest register to pin delay is 5.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y5\[0\]\$latch 1 REG LCCOMB_X32_Y8_N16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X32_Y8_N16; Fanout = 1; REG Node = 'y5\[0\]\$latch'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { y5[0]$latch } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.355 ns) + CELL(2.642 ns) 5.997 ns y5\[0\] 2 PIN PIN_T2 0 " "Info: 2: + IC(3.355 ns) + CELL(2.642 ns) = 5.997 ns; Loc. = PIN_T2; Fanout = 0; PIN Node = 'y5\[0\]'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.997 ns" { y5[0]$latch y5[0] } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 44.06 % ) " "Info: Total cell delay = 2.642 ns ( 44.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.355 ns ( 55.94 % ) " "Info: Total interconnect delay = 3.355 ns ( 55.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.997 ns" { y5[0]$latch y5[0] } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "5.997 ns" { y5[0]$latch {} y5[0] {} } { 0.000ns 3.355ns } { 0.000ns 2.642ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { key key~clk_delay_ctrl key~clkctrl y5[0]$latch } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { key {} key~combout {} key~clk_delay_ctrl {} key~clkctrl {} y5[0]$latch {} } { 0.000ns 0.000ns 0.091ns 0.000ns 1.367ns } { 0.000ns 0.862ns 0.155ns 0.000ns 0.150ns } "" } } { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.997 ns" { y5[0]$latch y5[0] } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "5.997 ns" { y5[0]$latch {} y5[0] {} } { 0.000ns 3.355ns } { 0.000ns 2.642ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "B1\[1\] S1\[2\] 17.381 ns Longest " "Info: Longest tpd from source pin \"B1\[1\]\" to destination pin \"S1\[2\]\" is 17.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns B1\[1\] 1 PIN PIN_T7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_T7; Fanout = 9; PIN Node = 'B1\[1\]'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1[1] } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.177 ns) + CELL(0.393 ns) 7.402 ns Add2~34 2 COMB LCCOMB_X64_Y8_N8 2 " "Info: 2: + IC(6.177 ns) + CELL(0.393 ns) = 7.402 ns; Loc. = LCCOMB_X64_Y8_N8; Fanout = 2; COMB Node = 'Add2~34'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.570 ns" { B1[1] Add2~34 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.473 ns Add2~36 3 COMB LCCOMB_X64_Y8_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 7.473 ns; Loc. = LCCOMB_X64_Y8_N10; Fanout = 2; COMB Node = 'Add2~36'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~34 Add2~36 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.544 ns Add2~38 4 COMB LCCOMB_X64_Y8_N12 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 7.544 ns; Loc. = LCCOMB_X64_Y8_N12; Fanout = 1; COMB Node = 'Add2~38'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~36 Add2~38 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 7.954 ns Add2~39 5 COMB LCCOMB_X64_Y8_N14 1 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 7.954 ns; Loc. = LCCOMB_X64_Y8_N14; Fanout = 1; COMB Node = 'Add2~39'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add2~38 Add2~39 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.171 ns) + CELL(0.420 ns) 10.545 ns LessThan1~33 6 COMB LCCOMB_X32_Y8_N30 5 " "Info: 6: + IC(2.171 ns) + CELL(0.420 ns) = 10.545 ns; Loc. = LCCOMB_X32_Y8_N30; Fanout = 5; COMB Node = 'LessThan1~33'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { Add2~39 LessThan1~33 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.393 ns) 11.209 ns Add4~11 7 COMB LCCOMB_X32_Y8_N8 2 " "Info: 7: + IC(0.271 ns) + CELL(0.393 ns) = 11.209 ns; Loc. = LCCOMB_X32_Y8_N8; Fanout = 2; COMB Node = 'Add4~11'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.664 ns" { LessThan1~33 Add4~11 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 11.619 ns Add4~12 8 COMB LCCOMB_X32_Y8_N10 8 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 11.619 ns; Loc. = LCCOMB_X32_Y8_N10; Fanout = 8; COMB Node = 'Add4~12'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add4~11 Add4~12 } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.964 ns) + CELL(2.798 ns) 17.381 ns S1\[2\] 9 PIN PIN_AD21 0 " "Info: 9: + IC(2.964 ns) + CELL(2.798 ns) = 17.381 ns; Loc. = PIN_AD21; Fanout = 0; PIN Node = 'S1\[2\]'" {  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.762 ns" { Add4~12 S1[2] } "NODE_NAME" } } { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.798 ns ( 33.36 % ) " "Info: Total cell delay = 5.798 ns ( 33.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.583 ns ( 66.64 % ) " "Info: Total interconnect delay = 11.583 ns ( 66.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.381 ns" { B1[1] Add2~34 Add2~36 Add2~38 Add2~39 LessThan1~33 Add4~11 Add4~12 S1[2] } "NODE_NAME" } } { "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "17.381 ns" { B1[1] {} B1[1]~combout {} Add2~34 {} Add2~36 {} Add2~38 {} Add2~39 {} LessThan1~33 {} Add4~11 {} Add4~12 {} S1[2] {} } { 0.000ns 0.000ns 6.177ns 0.000ns 0.000ns 0.000ns 2.171ns 0.271ns 0.000ns 2.964ns } { 0.000ns 0.832ns 0.393ns 0.071ns 0.071ns 0.410ns 0.420ns 0.393ns 0.410ns 2.798ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}