jian.map.qmsg

1、 掌握VHDL的结构以及实例的编程； 2、 学会使用QuartusⅡ平台的开化； 3、 设计一个2位BCD码加法器。

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y5\[3\] jian.vhd(39) " "Info (10041): Inferred latch for \"y5\[3\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y5\[4\] jian.vhd(39) " "Info (10041): Inferred latch for \"y5\[4\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y5\[5\] jian.vhd(39) " "Info (10041): Inferred latch for \"y5\[5\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y5\[6\] jian.vhd(39) " "Info (10041): Inferred latch for \"y5\[6\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y4\[0\] jian.vhd(39) " "Info (10041): Inferred latch for \"y4\[0\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y4\[1\] jian.vhd(39) " "Info (10041): Inferred latch for \"y4\[1\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y4\[2\] jian.vhd(39) " "Info (10041): Inferred latch for \"y4\[2\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y4\[3\] jian.vhd(39) " "Info (10041): Inferred latch for \"y4\[3\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y4\[4\] jian.vhd(39) " "Info (10041): Inferred latch for \"y4\[4\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y4\[5\] jian.vhd(39) " "Info (10041): Inferred latch for \"y4\[5\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y4\[6\] jian.vhd(39) " "Info (10041): Inferred latch for \"y4\[6\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S0\[0\]~3 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0\[0\]~3 that it feeds" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 14 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S0\[1\]~2 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0\[1\]~2 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S0\[2\]~1 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0\[2\]~1 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S0\[3\]~0 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0\[3\]~0 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S1\[0\]~3 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1\[0\]~3 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S1\[1\]~2 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1\[1\]~2 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S1\[2\]~1 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1\[2\]~1 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S1\[3\]~0 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1\[3\]~0 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "S2~0 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S2~0 that it feeds" {  } { { "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_HDR" "" "Info: One or more bidirs are fed by always enabled tri-state buffers" { { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S0\[0\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S0\[0\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S0\[1\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S0\[1\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S0\[2\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S0\[2\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S0\[3\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S0\[3\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S1\[0\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S1\[0\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S1\[1\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S1\[1\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S1\[2\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S1\[2\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S1\[3\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S1\[3\]\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "S2 " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"S2\" is moved to its source" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 10 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0}  } {  } 0 0 "One or more bidirs are fed by always enabled tri-state buffers" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IOPT_MLS_DUP_LATCH_INFO" "y6\[3\]\$latch y6\[0\]\$latch " "Info: Duplicate LATCH primitive \"y6\[3\]\$latch\" merged with LATCH primitive \"y6\[0\]\$latch\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "y6\[4\]\$latch y6\[0\]\$latch " "Info: Duplicate LATCH primitive \"y6\[4\]\$latch\" merged with LATCH primitive \"y6\[0\]\$latch\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "y6\[5\]\$latch y6\[0\]\$latch " "Info: Duplicate LATCH primitive \"y6\[5\]\$latch\" merged with LATCH primitive \"y6\[0\]\$latch\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "" 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "S0\[0\]~4 " "Warning: Node \"S0\[0\]~4\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S0\[1\]~5 " "Warning: Node \"S0\[1\]~5\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S0\[2\]~6 " "Warning: Node \"S0\[2\]~6\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S0\[3\]~7 " "Warning: Node \"S0\[3\]~7\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S1\[0\]~4 " "Warning: Node \"S1\[0\]~4\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S1\[1\]~5 " "Warning: Node \"S1\[1\]~5\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S1\[2\]~6 " "Warning: Node \"S1\[2\]~6\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S1\[3\]~7 " "Warning: Node \"S1\[3\]~7\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "S2~1 " "Warning: Node \"S2~1\"" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "y6\[1\] GND " "Warning (13410): Pin \"y6\[1\]\" stuck at GND" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "y6\[2\] GND " "Warning (13410): Pin \"y6\[2\]\" stuck at GND" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "y6\[6\] VCC " "Warning (13410): Pin \"y6\[6\]\" stuck at VCC" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "152 " "Info: Implemented 152 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "49 " "Info: Implemented 49 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "9 " "Info: Implemented 9 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "77 " "Info: Implemented 77 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 36 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 19 02:29:16 2008 " "Info: Processing ended: Thu Jun 19 02:29:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}