jian.map.qmsg

1、 掌握VHDL的结构以及实例的编程； 2、 学会使用QuartusⅡ平台的开化； 3、 设计一个2位BCD码加法器。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 19 02:29:09 2008 " "Info: Processing started: Thu Jun 19 02:29:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jian -c jian " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jian -c jian" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jian.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jian.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jian-one " "Info: Found design unit 1: jian-one" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 jian " "Info: Found entity 1: jian" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jian " "Info: Elaborating entity \"jian\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "T0 jian.vhd(20) " "Warning (10492): VHDL Process Statement warning at jian.vhd(20): signal \"T0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "T0 jian.vhd(27) " "Warning (10492): VHDL Process Statement warning at jian.vhd(27): signal \"T0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Z0 jian.vhd(27) " "Warning (10492): VHDL Process Statement warning at jian.vhd(27): signal \"Z0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C1 jian.vhd(28) " "Warning (10492): VHDL Process Statement warning at jian.vhd(28): signal \"C1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "T1 jian.vhd(29) " "Warning (10492): VHDL Process Statement warning at jian.vhd(29): signal \"T1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "T1 jian.vhd(36) " "Warning (10492): VHDL Process Statement warning at jian.vhd(36): signal \"T1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Z1 jian.vhd(36) " "Warning (10492): VHDL Process Statement warning at jian.vhd(36): signal \"Z1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C2 jian.vhd(37) " "Warning (10492): VHDL Process Statement warning at jian.vhd(37): signal \"C2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 37 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "key jian.vhd(93) " "Warning (10492): VHDL Process Statement warning at jian.vhd(93): signal \"key\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 93 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "S2 jian.vhd(120) " "Warning (10492): VHDL Process Statement warning at jian.vhd(120): signal \"S2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 120 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y4 jian.vhd(39) " "Warning (10631): VHDL Process Statement warning at jian.vhd(39): inferring latch(es) for signal or variable \"y4\", which holds its previous value in one or more paths through the process" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y5 jian.vhd(39) " "Warning (10631): VHDL Process Statement warning at jian.vhd(39): inferring latch(es) for signal or variable \"y5\", which holds its previous value in one or more paths through the process" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y6 jian.vhd(39) " "Warning (10631): VHDL Process Statement warning at jian.vhd(39): inferring latch(es) for signal or variable \"y6\", which holds its previous value in one or more paths through the process" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y6\[0\] jian.vhd(39) " "Info (10041): Inferred latch for \"y6\[0\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y6\[1\] jian.vhd(39) " "Info (10041): Inferred latch for \"y6\[1\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y6\[2\] jian.vhd(39) " "Info (10041): Inferred latch for \"y6\[2\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y6\[3\] jian.vhd(39) " "Info (10041): Inferred latch for \"y6\[3\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y6\[4\] jian.vhd(39) " "Info (10041): Inferred latch for \"y6\[4\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y6\[5\] jian.vhd(39) " "Info (10041): Inferred latch for \"y6\[5\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y6\[6\] jian.vhd(39) " "Info (10041): Inferred latch for \"y6\[6\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y5\[0\] jian.vhd(39) " "Info (10041): Inferred latch for \"y5\[0\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y5\[1\] jian.vhd(39) " "Info (10041): Inferred latch for \"y5\[1\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y5\[2\] jian.vhd(39) " "Info (10041): Inferred latch for \"y5\[2\]\" at jian.vhd(39)" {  } { { "jian.vhd" "" { Text "H:/jian2/jian.vhd" 39 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}