jian.map.rpt

1、 掌握VHDL的结构以及实例的编程； 2、 学会使用QuartusⅡ平台的开化； 3、 设计一个2位BCD码加法器。

; Maximum fan-out node                        ; key   ;
; Maximum fan-out                             ; 15    ;
; Total fan-out                               ; 320   ;
; Average fan-out                             ; 2.11  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |jian                      ; 77 (77)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 75   ; 0            ; |jian               ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; y6[0]$latch                                         ; key                 ; yes                    ;
; y6[3]$latch                                         ; key                 ; yes                    ;
; y6[4]$latch                                         ; key                 ; yes                    ;
; y6[5]$latch                                         ; key                 ; yes                    ;
; y5[0]$latch                                         ; key                 ; yes                    ;
; y5[1]$latch                                         ; key                 ; yes                    ;
; y5[2]$latch                                         ; key                 ; yes                    ;
; y5[3]$latch                                         ; key                 ; yes                    ;
; y5[4]$latch                                         ; key                 ; yes                    ;
; y5[5]$latch                                         ; key                 ; yes                    ;
; y5[6]$latch                                         ; key                 ; yes                    ;
; y4[0]$latch                                         ; key                 ; yes                    ;
; y4[1]$latch                                         ; key                 ; yes                    ;
; y4[2]$latch                                         ; key                 ; yes                    ;
; y4[3]$latch                                         ; key                 ; yes                    ;
; y4[4]$latch                                         ; key                 ; yes                    ;
; y4[5]$latch                                         ; key                 ; yes                    ;
; y4[6]$latch                                         ; key                 ; yes                    ;
; Number of user-specified and inferred latches = 18  ;                     ;                        ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jun 19 02:29:09 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jian -c jian
Info: Found 2 design units, including 1 entities, in source file jian.vhd
    Info: Found design unit 1: jian-one
    Info: Found entity 1: jian
Info: Elaborating entity "jian" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at jian.vhd(20): signal "T0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(27): signal "T0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(27): signal "Z0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(28): signal "C1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(29): signal "T1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(36): signal "T1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(36): signal "Z1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(37): signal "C2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(93): signal "key" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at jian.vhd(120): signal "S2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at jian.vhd(39): inferring latch(es) for signal or variable "y4", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at jian.vhd(39): inferring latch(es) for signal or variable "y5", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at jian.vhd(39): inferring latch(es) for signal or variable "y6", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "y6[0]" at jian.vhd(39)
Info (10041): Inferred latch for "y6[1]" at jian.vhd(39)
Info (10041): Inferred latch for "y6[2]" at jian.vhd(39)
Info (10041): Inferred latch for "y6[3]" at jian.vhd(39)
Info (10041): Inferred latch for "y6[4]" at jian.vhd(39)
Info (10041): Inferred latch for "y6[5]" at jian.vhd(39)
Info (10041): Inferred latch for "y6[6]" at jian.vhd(39)
Info (10041): Inferred latch for "y5[0]" at jian.vhd(39)
Info (10041): Inferred latch for "y5[1]" at jian.vhd(39)
Info (10041): Inferred latch for "y5[2]" at jian.vhd(39)
Info (10041): Inferred latch for "y5[3]" at jian.vhd(39)
Info (10041): Inferred latch for "y5[4]" at jian.vhd(39)
Info (10041): Inferred latch for "y5[5]" at jian.vhd(39)
Info (10041): Inferred latch for "y5[6]" at jian.vhd(39)
Info (10041): Inferred latch for "y4[0]" at jian.vhd(39)
Info (10041): Inferred latch for "y4[1]" at jian.vhd(39)
Info (10041): Inferred latch for "y4[2]" at jian.vhd(39)
Info (10041): Inferred latch for "y4[3]" at jian.vhd(39)
Info (10041): Inferred latch for "y4[4]" at jian.vhd(39)
Info (10041): Inferred latch for "y4[5]" at jian.vhd(39)
Info (10041): Inferred latch for "y4[6]" at jian.vhd(39)
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0[0]~3 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0[1]~2 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0[2]~1 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S0[3]~0 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1[0]~3 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1[1]~2 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1[2]~1 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S1[3]~0 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus S2~0 that it feeds
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S0[0]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S0[1]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S0[2]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S0[3]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S1[0]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S1[1]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S1[2]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S1[3]" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "S2" is moved to its source
Info: Duplicate LATCH primitives merged into single LATCH primitive
    Info: Duplicate LATCH primitive "y6[3]$latch" merged with LATCH primitive "y6[0]$latch"
    Info: Duplicate LATCH primitive "y6[4]$latch" merged with LATCH primitive "y6[0]$latch"
    Info: Duplicate LATCH primitive "y6[5]$latch" merged with LATCH primitive "y6[0]$latch"
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "S0[0]~4"
    Warning: Node "S0[1]~5"
    Warning: Node "S0[2]~6"
    Warning: Node "S0[3]~7"
    Warning: Node "S1[0]~4"
    Warning: Node "S1[1]~5"
    Warning: Node "S1[2]~6"
    Warning: Node "S1[3]~7"
    Warning: Node "S2~1"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "y6[1]" stuck at GND
    Warning (13410): Pin "y6[2]" stuck at GND
    Warning (13410): Pin "y6[6]" stuck at VCC
Info: Implemented 152 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 49 output pins
    Info: Implemented 9 bidirectional pins
    Info: Implemented 77 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 36 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Thu Jun 19 02:29:16 2008
    Info: Elapsed time: 00:00:07