jian.vhd

1、 掌握VHDL的结构以及实例的编程； 2、 学会使用QuartusⅡ平台的开化； 3、 设计一个2位BCD码加法器。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jian is
	port(key:in std_logic; 
	     A0,A1,B0,B1:in std_logic_vector(3 downto 0);
        y6,y5,y4,y3,y2,y1,y0:out std_logic_vector(6 downto 0);
        S0,S1:inout std_logic_vector(3 downto 0);
         S2:inout std_logic);
end entity;
architecture one of jian is
    signal C1,C2:std_logic;
    signal T1,T0:std_logic_vector(4 downto 0);
    signal Z1,Z0:std_logic_vector(3 downto 0);
    begin
	process(key,A0,A1,B0,B1)
	begin
		T0<=('0'&A0)+('0'&B0);
		if T0>"01001" then
		Z0<="1010";
			C1<='1';
			else
			Z0<="0000";
			C1<='0';
			end if;
			S0<=T0(3 downto 0)-Z0;
			T1<=('0'&A1)+('0'&B1)+C1;
			if T1>"01001" then
			Z1<="1010";
			C2<='1';
			else
			Z1<="0000";
			C2<='0';
			end if;
			S1<=T1(3 downto 0)-Z1;
		    S2<=C2;
			end process;	
	process(A0,A1,B0,B1,S1,S0)
		begin
		case A0 is
			when "0000" =>y0<="1000000";
			when "0001" =>y0<="1111001";
			when "0010" =>y0<="0100100";
			when "0011" =>y0<="0110000";
			when "0100" =>y0<="0011001";
			when "0101" =>y0<="0010010";
			when "0110" =>y0<="0000010";
			when "0111" =>y0<="1111000";
			when "1000" =>y0<="0000000";
			when "1001" =>y0<="0010000";
			when others =>y0<="1111111";
		end case;
		case A1 is
			when "0000" =>y1<="1000000";
			when "0001" =>y1<="1111001";
			when "0010" =>y1<="0100100";
			when "0011" =>y1<="0110000";
			when "0100" =>y1<="0011001";
			when "0101" =>y1<="0010010";
			when "0110" =>y1<="0000010";
			when "0111" =>y1<="1111000";
			when "1000" =>y1<="0000000";
			when "1001" =>y1<="0010000";
			when others =>y1<="1111111";
		end case;
		case B0 is
			when "0000" =>y2<="1000000";
			when "0001" =>y2<="1111001";
			when "0010" =>y2<="0100100";
			when "0011" =>y2<="0110000";
			when "0100" =>y2<="0011001";
			when "0101" =>y2<="0010010";
			when "0110" =>y2<="0000010";
			when "0111" =>y2<="1111000";
			when "1000" =>y2<="0000000";
			when "1001" =>y2<="0010000";
			when others =>y2<="1111111";
		end case;
		case B1 is
			when "0000" =>y3<="1000000";
			when "0001" =>y3<="1111001";
			when "0010" =>y3<="0100100";
			when "0011" =>y3<="0110000";
			when "0100" =>y3<="0011001";
			when "0101" =>y3<="0010010";
			when "0110" =>y3<="0000010";
			when "0111" =>y3<="1111000";
			when "1000" =>y3<="0000000";
			when "1001" =>y3<="0010000";
			when others =>y3<="1111111";
		end case;
		if  key='0' then
		case S0 is
			when "0000" =>y4<="1000000";
			when "0001" =>y4<="1111001";
			when "0010" =>y4<="0100100";
			when "0011" =>y4<="0110000";
			when "0100" =>y4<="0011001";
			when "0101" =>y4<="0010010";
			when "0110" =>y4<="0000010";
			when "0111" =>y4<="1111000";
			when "1000" =>y4<="0000000";
			when "1001" =>y4<="0010000";
			when others =>y4<="1111111";
		end case;
		case S1 is
			when "0000" =>y5<="1000000";
			when "0001" =>y5<="1111001";
			when "0010" =>y5<="0100100";
			when "0011" =>y5<="0110000";
			when "0100" =>y5<="0011001";
			when "0101" =>y5<="0010010";
			when "0110" =>y5<="0000010";
			when "0111" =>y5<="1111000";
			when "1000" =>y5<="0000000";
			when "1001" =>y5<="0010000";
			when others =>y5<="1111111";
		end case;
		case S2 is
			when '0' =>y6<="1000000";
			when  '1' =>y6<="1111001";
			when others =>y6<="ZZZZZZZ";
		end case;
		end if;
	end process;
end architecture;