dds.hif

verilog编写基于fpga的DDS实现

-1
3
cin8
-1
3
cin7
-1
3
cin6
-1
3
cin5
-1
3
cin4
-1
3
cin3
-1
3
cin2
-1
3
cin16
-1
3
cin15
-1
3
cin14
-1
3
cin13
-1
3
cin12
-1
3
cin11
-1
3
cin10
-1
3
cin1
-1
3
cin0
-1
3
}
# end
# entity
a_csnbuffer
# storage
db|dds.(14).cnf
db|dds.(14).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|a_csnbuffer.tdf
14fa1fe880ca66e7782a2fafd457197
6
# user_parameter {
WIDTH
17
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout0
-1
3
sin0
-1
3
ena
-1
3
clrn
-1
3
clk
-1
3
}
# end
# entity
addcore
# storage
db|dds.(15).cnf
db|dds.(15).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|addcore.tdf
a63b3f9948676dba45ce9d3335c98e4
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
17
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|altera|quartus60|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
..|..|altera|quartus60|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
}
# end
# entity
bypassff
# storage
db|dds.(16).cnf
db|dds.(16).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|bypassff.tdf
5a3ffc33a19f67d4f5edca6ceea08d60
6
# user_parameter {
WIDTH
17
PARAMETER_UNKNOWN
USR
}
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d16
-1
3
d15
-1
3
d14
-1
3
d13
-1
3
d12
-1
3
d11
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
}
# end
# entity
bypassff
# storage
db|dds.(17).cnf
db|dds.(17).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|bypassff.tdf
5a3ffc33a19f67d4f5edca6ceea08d60
6
# user_parameter {
WIDTH
17
PARAMETER_UNKNOWN
USR
}
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d16
-1
3
d15
-1
3
d14
-1
3
d13
-1
3
d12
-1
3
d11
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
}
# end
# entity
bypassff
# storage
db|dds.(18).cnf
db|dds.(18).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|bypassff.tdf
5a3ffc33a19f67d4f5edca6ceea08d60
6
# user_parameter {
WIDTH
2
PARAMETER_UNKNOWN
USR
}
# used_port {
q1
-1
3
q0
-1
3
ena
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clk
-1
3
}
# end
# entity
altshift
# storage
db|dds.(19).cnf
db|dds.(19).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|altshift.tdf
eedda481b22c659bfdc3e0a628220
6
# user_parameter {
WIDTH
32
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
altshift
# storage
db|dds.(20).cnf
db|dds.(20).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|altshift.tdf
eedda481b22c659bfdc3e0a628220
6
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result0
-1
3
data0
-1
3
}
# end
# entity
square
# storage
db|dds.(21).cnf
db|dds.(21).cnf
# case_insensitive
# source_file
square.tdf
4c4d19acd849d159c96247dbc9896c37
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
address9
-1
3
address8
-1
3
address7
-1
3
address6
-1
3
address5
-1
3
address4
-1
3
address3
-1
3
address2
-1
3
address11
-1
3
address10
-1
3
address1
-1
3
address0
-1
3
}
# include_file {
..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
}
# hierarchies {
square:inst2
}
# end
# entity
altsyncram
# storage
db|dds.(22).cnf
db|dds.(22).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_UNKNOWN
USR
WIDTHAD_A
12
PARAMETER_UNKNOWN
USR
NUMWORDS_A
4096
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
squra.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_b431
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
}
# hierarchies {
square:inst2|altsyncram:altsyncram_component
}
# end
# entity
cos_rom
# storage
db|dds.(25).cnf
db|dds.(25).cnf
# case_insensitive
# source_file
cos_rom.tdf
519e6bca539aa6df1cc4f7c3b02fff
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
address9
-1
3
address8
-1
3
address7
-1
3
address6
-1
3
address5
-1
3
address4
-1
3
address3
-1
3
address2
-1
3
address11
-1
3
address10
-1
3
address1
-1
3
address0
-1
3
}
# include_file {
..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
}
# hierarchies {
cos_rom:inst1
}
# end
# entity
altsyncram
# storage
db|dds.(26).cnf
db|dds.(26).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_UNKNOWN
USR
WIDTHAD_A
12
PARAMETER_UNKNOWN
USR
NUMWORDS_A
4096
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
cos.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ut41
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
}
# hierarchies {
cos_rom:inst1|altsyncram:altsyncram_component
}
# end
# entity
sld_mod_ram_rom
# storage
db|dds.(27).cnf
db|dds.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|sld_mod_ram_rom.vhd
cace3e25a569423fe6146c8930ac7b
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
135818752
PARAMETER_DEC
DEF
sld_ip_version
1
PARAMETER_DEC
DEF
sld_ip_minor_version
2
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
12
PARAMETER_UNKNOWN
USR
numwords
4096
PARAMETER_UNKNOWN
USR
widthad
12
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
000000000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
0
PARAMETER_UNKNOWN
USR
}
# hierarchies {
cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2
sin_rom:inst|altsyncram:altsyncram_component|altsyncram_3u41:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
sld_rom_sr
# storage
db|dds.(28).cnf
db|dds.(28).cnf