freqdivision.vhd

来自「实现了16*16点阵上的三色显示的弹球游戏」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
entity freqDivision is
	port (clk:in std_logic;
		scanClk:out std_logic;
		systemClk:out std_logic);
end freqDivision;

architecture main of freqDivision is
	
	component count16 
	port (clk:in std_logic;
		co:out std_logic;
		qcnt:buffer std_logic_vector(3 downto 0));
	end component;
	
	component count4 
	port (clk:in std_logic;
		co:out std_logic;
		qcnt:buffer std_logic_vector(1 downto 0));
	end component;
	
	signal tempcount1,tempcount3:std_logic_vector(3 downto 0);
	signal tempcount2:std_logic_vector(1 downto 0);
	signal temp1,temp2,temp3,temp4:std_logic;
	
	begin	
		scanClk<=tempcount3(1);
		u1: count16 port map(clk,temp1,tempcount1);
		u2: count16 port map(temp1,temp2,tempcount1);
		u3: count16 port map(temp2,temp3,tempcount3);
		u4: count16 port map(temp3,temp4,tempcount1);
		u5: count4	port map(temp4,systemClk,tempcount2);
	end main;