📄 pinball.map.rpt
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+-----------------------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------+
; |Pinball ; 4987 (4816) ; 390 ; 0 ; 92 ; 0 ; 4597 (4476) ; 39 (5) ; 351 (335) ; 8 (8) ; |Pinball ;
; |freqDivision:u4| ; 64 (0) ; 31 ; 0 ; 0 ; 0 ; 33 (0) ; 28 (0) ; 3 (0) ; 0 (0) ; |Pinball|freqDivision:u4 ;
; |count16:u1| ; 15 (15) ; 7 ; 0 ; 0 ; 0 ; 8 (8) ; 7 (7) ; 0 (0) ; 0 (0) ; |Pinball|freqDivision:u4|count16:u1 ;
; |count16:u2| ; 15 (15) ; 7 ; 0 ; 0 ; 0 ; 8 (8) ; 7 (7) ; 0 (0) ; 0 (0) ; |Pinball|freqDivision:u4|count16:u2 ;
; |count16:u3| ; 15 (15) ; 7 ; 0 ; 0 ; 0 ; 8 (8) ; 7 (7) ; 0 (0) ; 0 (0) ; |Pinball|freqDivision:u4|count16:u3 ;
; |count16:u4| ; 15 (15) ; 7 ; 0 ; 0 ; 0 ; 8 (8) ; 7 (7) ; 0 (0) ; 0 (0) ; |Pinball|freqDivision:u4|count16:u4 ;
; |count4:u5| ; 4 (4) ; 3 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 3 (3) ; 0 (0) ; |Pinball|freqDivision:u4|count4:u5 ;
; |input:u1| ; 4 (4) ; 2 ; 0 ; 0 ; 0 ; 2 (2) ; 2 (2) ; 0 (0) ; 0 (0) ; |Pinball|input:u1 ;
; |input:u2| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 2 (2) ; 0 (0) ; 0 (0) ; |Pinball|input:u2 ;
; |input:u3| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 2 (2) ; 0 (0) ; 0 (0) ; |Pinball|input:u3 ;
; |seg7dec:u5| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |Pinball|seg7dec:u5 ;
; |seg7dec:u6| ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 0 (0) ; |Pinball|seg7dec:u6 ;
; |state5:core| ; 93 (93) ; 13 ; 0 ; 0 ; 0 ; 80 (80) ; 0 (0) ; 13 (13) ; 0 (0) ; |Pinball|state5:core ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops ;
+--------------------------------------------------------+---+
; Logic Cell Name ; ;
+--------------------------------------------------------+---+
; input:u1|b~0 ; ;
; input:u2|b~0 ; ;
; input:u3|b~0 ; ;
; Number of logic cells representing combinational loops ; 3 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 390 ;
; Number of registers using Synchronous Clear ; 144 ;
; Number of registers using Synchronous Load ; 109 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 322 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 9:1 ; 4 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |Pinball|py[3] ;
; 9:1 ; 3 bits ; 18 LEs ; 3 LEs ; 15 LEs ; Yes ; |Pinball|dir[0]~reg0 ;
; 17:1 ; 16 bits ; 176 LEs ; 160 LEs ; 16 LEs ; Yes ; |Pinball|rowOut1[0] ;
; 11:1 ; 2 bits ; 14 LEs ; 2 LEs ; 12 LEs ; Yes ; |Pinball|nextState[2] ;
; 10:1 ; 2 bits ; 12 LEs ; 2 LEs ; 10 LEs ; Yes ; |Pinball|life[0] ;
; 12:1 ; 4 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |Pinball|px[0] ;
; 10:1 ; 2 bits ; 12 LEs ; 2 LEs ; 10 LEs ; Yes ; |Pinball|grade[0] ;
; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |Pinball|Mux~1111 ;
; 3:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |Pinball|Mux~1095 ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Pinball|Mux~193 ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Pinball|Mux~193 ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Pinball|Mux~174 ;
; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |Pinball|Mux~182 ;
; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |Pinball|Mux~176 ;
; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |Pinball|Mux~178 ;
; 5:1 ; 4 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |Pinball|Mux~146 ;
; 5:1 ; 4 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |Pinball|Mux~182 ;
; 10:1 ; 3 bits ; 18 LEs ; 15 LEs ; 3 LEs ; No ; |Pinball|Mux~1078 ;
; 1:1 ; 5 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |Pinball|add~1 ;
; 10:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |Pinball|Mux~156 ;
; 10:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |Pinball|Mux~193 ;
; 20:1 ; 2 bits ; 26 LEs ; 26 LEs ; 0 LEs ; No ; |Pinball|Mux~156 ;
; 20:1 ; 2 bits ; 26 LEs ; 26 LEs ; 0 LEs ; No ; |Pinball|Mux~193 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/Pinballv2/Pinball.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Mon Jun 04 09:49:58 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Pinball -c Pinball
Info: Found 2 design units, including 1 entities, in source file state5.vhd
Info: Found design unit 1: state5-main
Info: Found entity 1: state5
Info: Found 2 design units, including 1 entities, in source file count4.vhd
Info: Found design unit 1: count4-main
Info: Found entity 1: count4
Info: Found 2 design units, including 1 entities, in source file count16.vhd
Info: Found design unit 1: count16-main
Info: Found entity 1: count16
Info: Found 2 design units, including 1 entities, in source file freqDivision.vhd
Info: Found design unit 1: freqDivision-main
Info: Found entity 1: freqDivision
Info: Found 2 design units, including 1 entities, in source file input.vhd
Info: Found design unit 1: input-main
Info: Found entity 1: input
Info: Found 2 design units, including 1 entities, in source file Pinball.vhd
Info: Found design unit 1: Pinball-main
Info: Found entity 1: Pinball
Info: Found 2 design units, including 1 entities, in source file seg7dec.vhd
Info: Found design unit 1: seg7dec-ver3
Info: Found entity 1: seg7dec
Info: Elaborating entity "Pinball" for the top level hierarchy
Warning: Tied undriven net "m[4]" at Pinball.vhd(14) to 0
Info: Elaborating entity "input" for hierarchy "input:u1"
Info: Elaborating entity "freqDivision" for hierarchy "freqDivision:u4"
Info: Elaborating entity "count16" for hierarchy "freqDivision:u4|count16:u1"
Info: Elaborating entity "count4" for hierarchy "freqDivision:u4|count4:u5"
Info: Elaborating entity "seg7dec" for hierarchy "seg7dec:u5"
Info: Elaborating entity "state5" for hierarchy "state5:core"
Warning: Reduced register "state5:core|ch1[3]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "nextState[0]" merged to single register "nextState[2]"
Info: Duplicate registers merged to single register
Info: Duplicate register "nextState[1]" merged to single register "nextState[2]", power-up level changed
Warning: Output pins are stuck at VCC or GND
Warning: Pin "lifeOut[1]" stuck at GND
Warning: Pin "gradeOut[1]" stuck at GND
Warning: Pin "m[4]" stuck at GND
Warning: Pin "change1[3]" stuck at GND
Info: Implemented 5079 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 87 output pins
Info: Implemented 4987 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Processing ended: Mon Jun 04 09:53:41 2007
Info: Elapsed time: 00:03:44
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