📄 count4.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity count4 is
port(clk:in std_logic;
--en:in std_logic;
co:out std_logic;
qcnt:buffer std_logic_vector(1 downto 0));
end count4;
architecture main of count4 is
shared variable i:integer range 0 to 1:=0;
signal count:std_logic_vector(1 downto 0):=(others =>'0');
begin
qcnt<=count;
co<=qcnt(0) and qcnt(1);
process(clk)
begin
if(rising_edge(clk)) then
count(i)<=not count(i);
i:=1-i;
if(count(1)='1') and (count(0)='1')then
i:=0;
count<="00";
end if;
end if;
end process;
end main;
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